In a pipelined ADC, each stage operates on analog data for one sampling clock cycle (or, sometimes, half a cycle) and then passes the analog residue signal to the next stage. This is called a "pipelined" architecture because each stage will process data from the previous stage then pass it onto the next stage on a clock edge. A complete conversion takes several clock cycles, so there is a delay of several clock cycles between sampling and availability of the digital output. In most sampled data systems the throughput rate is important (the faster the better) but the conversion time is less so. But in some systems this conversion delay may be unacceptable and other converter types must be used.