The flash converter makes use of parallel comparators, each operating at a slightly different reference voltage determined by the resistor ladder network. An N-bit flash converter requires 2N-1 latched comparators, therefore the technique is rarely used beyond 8-bits. The comparators are latched simultaneously, therefore a separate SHA is not generally required. However, mismatches in timing between the comparators may require an external SHA for optimum performance at high input slew rates. The output of the comparator bank is a thermometer code, which is decoded into the proper binary code by the decoding logic. Conceptually, the decoding logic is a priority encoder, but it may be more complicated to correct for comparator metastable state errors.