Subranging ADCs were first documented in the mid 1950s. This diagram shows a two-stage subranging ADC, but the concept can be continued to additional stages. A single stage can also be used a number of times by "recirculating" the analog data using switches and a PGA. There is a "coarse" conversion of N1 bits followed by a "fine" conversion of N2 bits. The individual sub-ADCs (labeled SADC) are generally flash converters, but do not have to be. Subranging ADCs do not necessarily have to be pipelined, but many are. On the other hand, most pipelined ADCs are subranging types. The N1-bit coarse conversion is converted back to analog by an N1 bit SDAC, subtracted from the held analog signal, amplified, and applied to the N2-bit SADC. Note that the N1 bit SADC and SDAC must be accurate to better than N1 + N2 bits, even though their resolution is less. This type of ADC can be analyzed better by examining the "residue signal" in the second stage.