The basic SAR algorithm was known by mathematicians in the 1500s. It was the solution to a problem of using a balance scale and binary weights to determine an unknown weight in a minimum number of operations. The first vacuum tube SAR ADCs were documented by Bell Labs in the 1940s in the Bell System Technical Journals. Bernard Gordon produced the first commercial vacuum tube SAR ADC in 1954, which was 11-bits at 50kSPS.  Gordon went on to patent the logic for performing the SAR algorithm in a 1958 patent application. The control logic (SAR) became an IC chip in the early 1970s (2503, 2504) and was offered by AMD and National. This was a popular building block in modular and hybrid ADCs. The input to the SAR converter must remain constant during the conversion cycle, therefore a SHA is required to process AC signals. The SAR ADC starts out with the DAC at mid-scale, and the comparator decides if the input is above or below mid-scale. The result is stored in the register, and the next bit is tested in the same manner. A 12-bit SAR ADC requires 12 conversion cycles. At the end of the conversion, an EOC, DRDY, or BUSY (not) is asserted. The basic accuracy of the SAR ADC is determined by the internal DAC.