74AUP Series Logic Gates

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            74AUP Series Logic Gates
                    Nexperia’s advanced ultra-low power (AUP) logic family provides ultra-low power in a small footprint
    

Image of Nexperia’s 74AUP Series Logic Gates Nexperia’s 74AUP family is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V_CC range.

Features
Wide supply voltage ranges from 2.3 V to 3.6 V High noise immunity ESD protection HBM JESD22-A114F Class 3 A exceeds 5,000 V CDM JESD22-C101E exceeds 1,000 V Low static power consumption; I_CC = 1.5 µA (max) Specified from -40°C to +85°C and -40°C to +125°C		Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V_CC I_OFF circuitry provides partial power-down mode operation Multiple package options
Applications
Mobile phones PDAs Digital cameras		Media players Portable medical devices Other handheld, power-sensitive applications