FCP(F)20N60 Datasheet by onsemi

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August 2014
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
1
FCP20N60 / FCPF20N60
N-Channel SuperFET® MOSFET
600 V, 20 A, 190 mΩ
Features
650V @ TJ = 150°C
•Typ. R
DS(on) = 150 mΩ
Ultra Low Gate Charge (Typ. Qg = 75 nC )
Low Effective Output Capacitance (Typ. Coss(eff.) = 165 pF )
100% Avalanche Tested
Applications
Solar Inverter
AC-DC Power Supply
Description
SuperFET® MOSFET is Fairchild Semiconductor’s first genera-
tion of high voltage super-junction (SJ) MOSFET family that is
utilizing charge balance technology for outstanding low on-
resistance and lower gate charge performance. This technology
is tailored to minimize conduction loss, provide superior switch-
ing performance, dv/dt rate and higher avalanche energy. Con-
sequently, SuperFET MOSFET is very suitable for the switching
power applications such as PFC, server/telecom power, FPD
TV power, ATX power and industrial power applications.
TO-220
GDSTO-220F
GDS
G
S
D
Absolute Maximum Ratings
*Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol Parameter FCP20N60 FCPF20N60 Unit
VDSS Drain-Source Voltage 600 V
IDDrain Current - Continuous (TC = 25°C)
- Continuous (TC = 100°C)
20
12.5
20*
12.5*
A
A
IDM Drain Current - Pulsed (Note 1) 60 60* A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 690 mJ
IAR Avalanche Current (Note 1) 20 A
EAR Repetitive Avalanche Energy (Note 1) 20.8 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns
PDPower Dissipation (TC = 25°C)
- Derate Above 25°C
208
1.67
39
0.3
W
W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum Lead Temperature for Soldering,
1/8” from Case for 5 Seconds 300 °C
Symbol Parameter FCP20N60 FCPF20N60 Unit
RθJC Thermal Resistance, Junction-to-Case 0.6 3.2 °C/W
RθJA Thermal Resistance, Junction-to-Ambient 62.5 62.5 °C/W
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
2
Package Marking and Ordering Information
Electrical Characteristics TC = 25oC unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity
FCP20N60 FCP20N60 TO-220 Tube N/A N/A 50 units
FCPF20N60 FCPF20N60 TO-220F Tube N/A N/A 50 units
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V, TJ = 25oC 600 - - V
ID = 250 μA, VGS = 0 V, TJ = 150oC- 650 - V
ΔBVDSS
/ ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, Referenced to 25oC-0.6-V/
oC
BVDS
Drain-Source Avalanche Breakdown
Voltage VGS = 0 V, ID = 20 A - 700 - V
IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V - - 1 μA
VDS = 480 V, TC = 125oC--10
IGSS Gate to Body Leakage Current VGS = ±30 V, VDS = 0 V - - ±100 nA
VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250 μA3.0-5.0V
RDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 10 A - 0.15 0.19 Ω
gFS Forward Transconductance VDS = 40 V, ID = 10 A - 17 - S
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1 MHz
- 2370 3080 pF
Coss Output Capacitance - 1280 1665 pF
Crss Reverse Transfer Capacitance - 95 - pF
Coss Output Capacitance VDS = 480 V, VGS = 0 V, f = 1 MHz - 65 85 pF
Coss(eff.) Effective Output Capacitance VDS = 0 V to 400 V, VGS = 0 V - 165 - pF
QgTotal Gate Charge at 10V VDS = 480 V, ID = 20 A,
VGS = 10 V
(Note 4)
-7598nC
Qgs Gate to Source Gate Charge - 13.5 18 nC
Qgd Gate to Drain “Miller” Charge - 36 - nC
td(on) Turn-On Delay Time
VDD = 300 V, ID = 20 A,
VGS = 10 V, RG = 25 Ω
(Note 4)
- 62 135 ns
trTurn-On Rise Time - 140 290 ns
td(off) Turn-Off Delay Time - 230 470 ns
tfTurn-Off Fall Time - 65 140 ns
ISMaximum Continuous Drain to Source Diode Forward Current - - 20 A
ISM Maximum Pulsed Drain to Source Diode Forward Current - - 60 A
VSD Drain to Source Diode Forward Voltage VGS = 0 V, ISD = 20 A - - 1.4 V
trr Reverse Recovery Time VGS = 0 V, ISD = 20 A,
dIF/dt = 100 A/μs
- 530 - ns
Qrr Reverse Recovery Charge - 10.5 - μC
Notes:
1: Repetitive rating: pulse-width limited by maximum junction temperature.
2: IAS = 10 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25°C.
3: ISD 20 A, di/dt 200 A/μs, VDD BVDSS, starting TJ = 25°C.
4: Essentially independent of operating temperature typical characteristics.
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
3
Typical Performance Characteristics
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperatue
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
10-1 100101
100
101
102
VGS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
Notes :
1. 250μs Pulse Test
2. TC = 25°C
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
246810
100
101
102
Note
1. VDS = 40V
2. 250μs Pulse Test
-55°C
150°C
25°C
ID , Drain Current [A]
VGS , Gate-Source Voltage [V]
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
0.0
0.1
0.2
0.3
0.4
VGS = 20V
VGS = 10V
Note : TJ = 25°C
RDS(ON) [Ω],
Drain-Source On-Resistance
ID, Drain Current [A]
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
100
101
102
25°C
150°C
Notes :
1. VGS = 0V
2. 250μs Pulse Test
IDR , Reverse Drain Current [A]
VSD , Source-Drain Voltage [V]
10-1 100101
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
0 1020304050607080
0
2
4
6
8
10
12
VDS = 250V
VDS = 100V
VDS = 400V
Note : ID = 20A
VGS, Gate-Source Voltage [V]
QG, Total Gate Charge [nC]
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
4
Typical Performance Characteristics (Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
Figure 9-1. Maximum Safe Operating Area Figure 9-2. Maximum Safe Operating Area
for FCP20N60 for FCPF20N60
Figure 10. Maximum Drain Current
vs. Case Temperature
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1. VGS = 0 V
2. ID = 250μA
BVDSS, (Normalized)
Drain-Source Breakdown Voltage
TJ, Junction Temperature [°C]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. VGS = 10 V
2. ID = 20 A
RDS(ON), (Normalized)
Drain-Source On-Resistance
TJ, Junction Temperature [°C]
100101102103
10-2
10-1
100
101
102
Operation in This Area
is Limited by R DS(on)
DC
10 ms
1 ms
100 us
Notes :
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
100101102103
10-2
10-1
100
101
102
100 us
DC
100 ms
10 ms
1 ms
Operation in This Area
is Limited by R DS(on)
Notes :
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
25 50 75 100 125 150
0
5
10
15
20
25
ID, Drain Current [A]
TC, Case Temperature [°C]
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
5
Typical Performance Characteristics (Continued)
Figure 11-1. Transient Thermal Response Curve for FCP20N60
Figure 11-2. Transient Thermal Response Curve for FCPF20N60
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
Notes :
1. ZθJC(t) = 0.6°C/W Max.
2. Duty Facto r, D=t1/t2
3. TJM - TC = PDM * ZθJC(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC(t), Thermal Response
t1, Square W ave Pulse D uration [sec]
t1
PDM
t2
t
1
, Rectangular Pulse Duration [sec]
Z
θ
JC
(t), Thermal Response [
o
C/W]
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
N otes :
1. ZθJC(t) =3.2°C/W Max.
2. D u ty Facto r, D=t1/t2
3. TJM - TC = PDM * ZθJC(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC(t), Thermal Response
t1, Square W ave Pulse Duration [sec]
t1
PDM
t2
t
1
, Rectangular Pulse Duration [sec]
Z
θ
JC
(t), Thermal Response [
o
C/W]
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
6
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
VGS
VGS
Figure 12. Gate Charge Test Circuit & Waveform
Figure 13. Resistive Switching Test Circuit & Waveforms
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS
RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS
RL
DUT
RG
VGS
VGS
IG = const.
FCP20N60 / FCPF20N60 — N-Channel SuperFET® MOSFET
©2008 Fairchild Semiconductor Corporation
FCP20N60 / FCPF20N60 Rev. C0
www.fairchildsemi.com
7
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
10.67
9.65
16.30
13.90
3.40
2.50
1.62
1.10
6.69
6.06
"A1"
4.70
4.00
2.85
2.10
0.60
0.36
14.04
12.70

3.50




9.40
8.13
14.30
11.50
8.65
7.59
3 2 1
1 2 3
NOTES:
A) REFERENCE JEDEC, TO-220, VARIATION AB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS COMMON TO ALL PACKAGE
SUPPLIERS EXCEPT WHERE NOTED [ ].
D) LOCATION OF MOLDED FEATURE MAY VARY
(LOWER LEFT CORNER, LOWER CENTER
AND CENTER OF THE PACKAGE)
E DOES NOT COMPLY JEDEC STANDARD VALUE.
F) "A1" DIMENSIONS AS BELOW:
SINGLE GAUGE = 0.51 - 0.61
DUAL GAUGE = 1.10 - 1.45
G) DRAWING FILE NAME: TO220B03REV9
H PRESENCE IS SUPPLIER DEPENDENT
I) SUPPLIER DEPENDENT MOLD LOCKING HOLES
IN HEATSINK.
C
16.51
15.42
[2.46]
SUPPLIER "A" PACKAGE
SHAPE
SUPPLIER "B" PACKAGE
SHAPE
1.00
0.55
SEE NOTE "F"
E
E
E
E
2.67
2.40
2.13
2.06
OPTIONAL
CHAMFER
1.62
1.42 H
IF PRESENT, SEE NOTE "D"
NOTE "I"
FRONT VIEWS
BOTTOM VIEW
BACK VIEW
SIDE VIEW
4.10
2.70
3.28 +( 7.00 )a f $3 08 i . (0.7 ) G Cf) iSEE NOTE "F" *7 1 6.88 6.48 {+3 G? " 1 x 45° G} V .00 .50 — (3.23)A 1 3 — 1.47 ( 2 14 )7 ‘ 1 24 2'9 . . 2.5 0.05 45 A 0.60 0.45 2.54 2.54 I OHS-imam w A 4.90 4.50 ES:
B
4.90
4.50
16.00
15.60
10.05
9.45
3.40
3.20
3.28
3.08
B
10.36
9.96
1.47
1.24
0.90
0.70
0.45
0.25
30°
2.54 2.54
7.00
2.14
(3.23)
B
13
SEE NOTE "F"
0.50
M
A
A
B
2.66
2.42
B
16.07
15.67
2.96
2.56
B
0.60
0.45
0.70
6.88
6.48
1 X
45°
SEE NOTE "F"
NOTES:
A. EXCEPT WHERE NOTED CONFORMS TO
EIAJ SC91A.
B
DOES NOT COMPLY EIAJ STD. VALUE.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS.
E. DIMENSION AND TOLERANCE AS PER ASME
Y14.5-1994.
F. OPTION 1 - WITH SUPPORT PIN HOLE.
OPTION 2 - NO SUPPORT PIN HOLE.
G. DRAWING FILE NAME: TO220M03REV5
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www mm cumrsuerguwaxem Mavkmg gm
www.onsemi.com
1
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coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
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