SN74LVC1G07-Q1 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G07-Q1
SCES826B –MARCH 2011–REVISED OCTOBER 2019
SN74LVC1G07-Q1 Single Buffer/Driver With Open-Drain Output
1
1 Features
1• Qualified for automotive applications
• AEC-Q100 Qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature
– 2000-V Device human-body model (HBM)
ESD classification level 2
– 1000-V Device charged-device model (CDM)
ESD classification level C5
• Supports 5-V VCC operation
• Input and open-drain output accept
Voltages up to 5.5 V
• Max tpd of 5.7 ns at 3.3 V
• Low power consumption, 10-μA max ICC
• ±24-mA Output drive at 3.3 V
• Ioff Supports partial-power-down mode
Operation
2 Applications
• Automotive infotainment
• Automotive ADAS camera and fusion
• Automotive body control module AV receiver
• Automotive HEV/powertrain
• Blu-ray player and home theater
• DVD recorder and player
• Desktop or notebook PC
• Digital radio or internet radio player
• Digital video camera (DVC)
• Embedded PC
• GPS: Personal navigation device
• Mobile internet device
• Network projector front end
• Portable media player
• Pro Audio Mixer
• Smoke detector
• Solid state drive (SSD): enterprise
• High-definition (HDTV)
• Tablet: enterprise
• Audio dock: portable
• DLP front projection system
• DVR and DVS
• Digital picture frame (DPF)
• Digital still camera
3 Description
The SN74LVC1G07-Q1 is a single channel open-
drain buffer/driver qualified for automotive
applications. This is designed for 1.65-V to 5.5-V VCC
operation.
The output of the SN74LVC1G07-Q1 device is open
drain and can be connected to other open-drain
outputs to implement active-low wired-OR or active-
high wired-AND functions. The maximum sink current
is 32 mA.
This device is fully specified for partial-power-down
applications using Ioff.The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
SN74LVC1G07-Q1
SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
SON (6) 1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
2
SN74LVC1G07-Q1
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics ......................................... 5
6.7 Operating Characteristics.......................................... 5
6.8 Typical Characteristics.............................................. 5
7 Parameter Measurement Information (Open
Drain)....................................................................... 6
7.1 PMI............................................................................ 6
8 Detailed Description.............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
9 Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application .................................................... 8
10 Power Supply Recommendations ....................... 9
11 Layout..................................................................... 9
11.1 Layout Guidelines ................................................... 9
11.2 Layout Example ...................................................... 9
12 Device and Documentation Support ................. 10
12.1 Receiving Notification of Documentation Updates 10
12.2 Community Resources.......................................... 10
12.3 Trademarks........................................................... 10
12.4 Electrostatic Discharge Caution............................ 10
12.5 Glossary................................................................ 10
13 Mechanical, Packaging, and Orderable
Information ........................................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2017) to Revision B Page
• Added DRY package option to Device Information table ...................................................................................................... 1
• Added DRY package as Product Preview device option to Pin Configuration and Functions .............................................. 3
• Added DRY package to Thermal Information table................................................................................................................ 4
Changes from Original (March 2011) to Revision A Page
• Added Applications,Device Information table, ESD Ratings table, Typical Characteristics,Feature Description
section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section. ............................................................................................................................................................... 1
• Changed RθJA value for DBV (SOT-23) package from: 206 to: 269.3 ................................................................................... 4
l TEXAS INSTRUMENTS
2
5
34Y
1
A
GND
N.C. VCC
AN.C.
N.C. 6
5
4
2
3
GND Y
VCC
1
3
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5 Pin Configuration and Functions
DBV or DCK Package
5-Pin SOT-23 or SC70
Top View
DRY Package
6-Pin SON
Transparent Top View
N.C. – No internal connection
See mechanical drawings for dimensions.
Pin Functions
PIN DESCRIPTION
NAME DBV, DCK DRY
N.C. 1 1, 5 Not connected
A 2 2 Input
GND 3 3 Ground
Y 4 4 Output
VCC 5 6 Power Pin
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage(2) –0.5 6.5 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage range applied to any output in the high or low state(2)(3) –0.5 6.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJOperating junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
l TEXAS INSTRUMENTS
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(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VIH High-level input voltage
VCC = 1.65 V to 1.95 V 0.65 × VCC
V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VIL Low-level input voltage
VCC = 1.65 V to 1.95 V 0.35 × VCC
V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 5.5 V
IOL Low-level output current
VCC = 1.65 V 4
mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
Δt/Δv Input transition rise or fall rate
VCC = 1.8 V ±0.15 V, 2.5 V ± 0.2 V 20
ns/VVCC = 3.3 V ± 0.3 V 10
VCC = 5 V ± 0.5 V 5
TAOperating free-air temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74LVC1G07-Q1
UNITDBV (SOT-23) DCK (SC70) DRY (SON)
5 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 269.3 301.2 439 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 175.2 186.5 277 °C/W
RθJB Junction-to-board thermal resistance 104.9 111.8 271 °C/W
ψJT Junction-to-top characterization parameter 73.4 78.3 84 °C/W
ψJB Junction-to-board characterization parameter 104.5 110.6 271 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – – – °C/W
l TEXAS INSTRUMENTS 25 5
Temperature - °C
TPD - ns
-100 -50 0 50 100 150
0
0.5
1
1.5
2
2.5
D001
TPD
5
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(1) All typical values are at VCC = 3.3 V, TA= 25°C.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VOL
IOL = 100 μA 1.65 V to 5.5 V 0.1
V
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA 3 V 0.4
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
IIA input VI= 5.5 V or GND 0 to 5.5 V ±5 μA
Ioff VIor VO= 5.5 V 0 ±10 μA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 μA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 μA
CiVI= VCC or GND 3.3 V 4 pF
CoVO= VCC or GND 3.3 V 5 pF
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.4 9.8 1 7.0 1.5 5.7 1 4.9 ns
6.7 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 3 3 4 6 pF
6.8 Typical Characteristics
Figure 1. TPD Across Temperature at 3.3V Vcc Figure 2. TPD Across Vcc at 25°C
l TEXAS INSTRUMENTS 510 From ompm Under Test CL (see Note A) LOAD CIRCUIT ‘n—o
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at VLOAD
(see Note B)
VOL
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VLOAD/2 − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
INPUT
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
tPHZ/tPZH
VLOAD
VLOAD
VLOAD
TEST S1
VLOAD/2
6
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7 Parameter Measurement Information (Open Drain)
7.1 PMI
Figure 3. Load Circuit And Voltage Waveforms
l TEXAS INSTRUMENTS
A
4Y
2
7
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8 Detailed Description
8.1 Overview
The SN74LVC1G07-Q1 device contains one open-drain buffer with a maximum sink current of 32 mA. This
device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
• Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
• Allows down-voltage translation.
• Inputs and outputs accept voltages to 5.5 V.
• Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74LVC1G07-Q1.
Table 1. Function Table
INPUT
AOUTPUT
Y
L L
H Z
l TEXAS INSTRUMENTS Bufler Fundmn Basm LED Dnver
uC or Logic
Basic LED Driver
Wired OR
uC or Logic
Buffer Function
uC or Logic
VPU
uC or Logic
VPU
LVC1G07
LVC1G07
LVC1G07
VCC
8
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G07-Q1 is a high drive CMOS device that can be used to implement a high output drive buffer,
such as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high drive and wired-
OR/AND functions. It is good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it
to translate up/down to VCC.
9.2 Typical Application
Figure 5. Typical Application-SN74LVC1G07-Q1
9.2.1 Design Requirements
This device uses CMOS technology and has high-output drive. Care should be taken to avoid bus contention
because it may drive currents that would exceed maximum limits. The high drive also creates fast edges into
light loads; so, routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are over-voltage tolerant allowing them to go as high as (VImax) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed (IOmax) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
l TEXAS INSTRUMENTS 1600
VCC
Unused Input
Input
Output Output
Input
Unused Input
Frequency - MHz
Icc - µA
0 20 40 60 80
0
200
400
600
800
1000
1200
1400
1600
D001
Icc 1.8V
Icc 2.5V
Icc 3.3V
Icc 5V
9
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Typical Application (continued)
– Outputs should not be pulled above 5.5 V.
9.2.3 Application Curve
Figure 6. Icc vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is
recommended for devices with a single supply. If there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally, they are tied to GND or VCC, whichever is more convenient.
11.2 Layout Example
Figure 7. Layout Example
l TEXAS INSTRUMENTS Am
10
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G07QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CCQO
SN74LVC1G07QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 16J
SN74LVC1G07QDCKTQ1 ACTIVE SC70 DCK 5 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 16J
SN74LVC1G07QDRYRQ1 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G07-Q1 :
•Catalog: SN74LVC1G07
•Enhanced Product: SN74LVC1G07-EP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G07QDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G07QDCKRQ1 SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G07QDCKTQ1 SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G07QDRYRQ1 SON DRY 6 5000 180.0 9.5 1.2 1.65 0.7 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G07QDBVRQ1 SOT-23 DBV 5 3000 200.0 183.0 25.0
SN74LVC1G07QDCKRQ1 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G07QDCKTQ1 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G07QDRYRQ1 SON DRY 6 5000 189.0 185.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
$ DRYOOOGB 1® A® as) 5@ “““+“““ L)
www.ti.com
PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
6X 0.35
0.25
2X
1
0.55 MAX
0.05
0.00
3X 0.6
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222207/B 02/2016
USON - 0.55 mm max heightDRY0006B
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
DRYOOOGB ““““““““““
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
6X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R ) TYP0.05
4222207/B 02/2016
USON - 0.55 mm max heightDRY0006B
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
DRYOOOGB
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R ) TYP0.05
4222207/B 02/2016
USON - 0.55 mm max heightDRY0006B
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
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