LMH0395 Datasheet by Texas Instruments

Datasheet Feedback/Errors

I TEXAS INSTRUMENTS

AEC+

Equalizer

Filter

AEC-

MUTE

MUTEREF

Restoration/

Level Control

Automatic

Equalization

Control

SDI

SDO0

BYPASS

Output

Drivers

MUTEREF

Energy

Detect Energy

Detect

AUTO SLEEP

Carrier

Detect

SPI_EN

SPI Control

De-Emphasis

Control

SDO1

SDO1_

DISABLE

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

LMH0395 3G HD/SD SDI Dual Output Low Power

Extended Reach Adaptive Cable Equalizer

(1) Due to SMPTE naming convention, all SMPTE Engineering

Documents will be numbered as a two-letter prefix and a

number. Documents and references with the same root

number and year are functionally identical; for example ST

424-2006 and SMPTE 424M-2006 refer to the same

document.

1 Features

1• ST 424, ST 292, ST 344, ST 259, and DVB-ASI

Compliant(1)

• Equalized Cable Lengths (Belden 1694A): 200

Meters at 2.97 Gbps, 220 Meters at 1.485 Gbps,

and 400 Meters at 270 Mbps

• Ultra-low Power Consumption: 140 mW (Dual

Outputs), 115 mW (Single Output)

• Dual Differential Outputs; Second Output Can Be

Independently Powered Down

• Power-Save Mode With Auto Sleep Control (17-

mW Typical Power Consumption in Power-Save

Mode)

• Designed for Crosstalk Immunity

• Output De-Emphasis to Compensate for FR4

Board Trace Losses

• Digital and Analog Programmable MUTEREF

Threshold

• Optional SPI Register Access and Pin Mode

Operation

• Input Data Rates: 125 Mbps to 2.97 Gbps

• Internally Terminated 100-ΩLVDS Outputs With

Programmable Output Common-Mode Voltage

and Swing

• Programmable Launch Amplitude Optimization

• Cable Length Indicator

• Single 2.5-V Supply Operation

• 24-Pin WQFN Package

• Industrial Temperature Range: −40°C to +85°C

2 Applications

• ST 424, ST 292, ST 344, and ST 259 Serial

Digital Interfaces(1)

• Broadcast Video Routers, Switchers, and

Distribution Amplifiers

3 Description

The LMH0395 3-Gbps HD/SD SDI Dual Output Low

Power Extended Reach Adaptive Cable Equalizer is

designed to equalize data transmitted over cable (or

any media with similar dispersive loss

characteristics). The equalizer operates over a wide

range of data rates from 125 Mbps to 2.97 Gbps and

supports ST 424, ST 292, ST 344, ST 259, and DVB-

ASI standards.

The LMH0395 device provides extended cable reach

with improved immunity to crosstalk and ultra low

power consumption. The equalizer includes active

sensing circuitry that ensures robust performance and

enhanced immunity to variations in the input signal

launch amplitude. The LMH0395 offers power

management to further reduce power consumption

when no input signal is present.

The LMH0395 has two differential serial data outputs,

increasing flexibility and eliminating the need for a

fanout buffer on the output in many applications. The

outputs may be independently enabled and

controlled. The output drivers offer programmable de-

emphasis for up to 40 inches of FR4 trace losses.

The LMH0395 supports two modes of operation. In

pin mode, the LMH0395 operates with control pins to

set its operating state. In SPI mode, an optional SPI

serial interface can be used to access and configure

multiple LMH0395 devices in a daisy-chain

configuration.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMH0395 WQFN (24) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

l TEXAS INSTRUMENTS

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 DC Electrical Characteristics .................................... 6

6.6 AC Electrical Characteristics..................................... 7

6.7 Switching Characteristics for SPI Interface............... 8

6.8 Timing Requirements for SPI Interface..................... 8

6.9 Typical Characteristics............................................ 10

7 Detailed Description............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 14

7.5 Programming........................................................... 14

7.6 Register Maps......................................................... 19

8 Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Application .................................................. 23

8.3 Dos and Don'ts........................................................ 24

9 Power Supply Recommendations...................... 25

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Examples................................................... 26

11 Device and Documentation Support ................. 27

11.1 Documentation Support ....................................... 27

11.2 Receiving Notification of Documentation Updates 27

11.3 Community Resources.......................................... 27

11.4 Trademarks........................................................... 27

11.5 Electrostatic Discharge Caution............................ 27

11.6 Glossary................................................................ 27

12 Mechanical, Packaging, and Orderable

Information ........................................................... 27

4 Revision History

Changes from Revision M (July 2015) to Revision N Page

• Changed MUTEREF pin description for both WQFN (Non-SPI) and WQFN SPI Mode packages.......................................... 3

• Changed sentence 'In pin mode, SPI_EN is driven logic low.' to 'Driving SPI_EN low enables pin mode.' to SPI

Control description................................................................................................................................................................ 12

Changes from Revision L (April 2013) to Revision M Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

l TEXAS INSTRUMENTS

LMH0395

107 8 9

2124 23 22

VEE

SDI

AUTO SLEEP

SPI_EN

1211

BYPASS

14 SDO0

1920

MUTE

VEE

SDI

VEE

AEC+

AEC-

SDO1_DISABLE

MUTEREF

VEE

SDO0

VEE

SDO1

VCC

VEE

DAP = VEE

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

5 Pin Configuration and Functions

RUM Package

24-Pin WQFN (Non-SPI)

Top View

(1) The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.

Pin Functions – Pin Mode (Non-SPI) / SPI_EN = GND(1)

PIN TYPE DESCRIPTION

NO. NAME

1 VEE Ground Negative power supply (ground)

2 VEE Ground Negative power supply (ground)

3 SDI I, Analog Serial data true input

4 SDI I, Analog Serial data complement input

5 VEE Ground Negative power supply (ground)

6 SPI_EN I, LVCMOS

SPI register access enable

This pin has an internal pulldown.

H = SPI register access mode

L = Pin mode

7 SDO1_DISABLE I, LVCMOS

Output driver 1 (SDO1, SDO1) disable

This pin has an internal pullup.

H (or no connection) = Output driver 1 is in a high-impedance state

L = Output driver 1 is enabled

8 AEC+ I/O, Analog AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional)

9 AEC- I/O, Analog AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional)

10 BYPASS I, LVCMOS

Equalization bypass

This pin has an internal pulldown.

H = Equalization is bypassed (no equalization occurs).

L = Normal operation

11 MUTEREF I, Analog Mute reference input that sets the threshold for CD and determines the maximum cable to

be equalized before muting. MUTEREF may be either unconnected or connected to

ground for normal CD operation. There is no MUTE in SPI Mode.

12 VEE Ground Negative power supply (ground)

13 VEE Ground Negative power supply (ground)

14 SDO0 O, LVDS Serial data output 0 complement

15 SDO0 O, LVDS Serial data output 0 true

16 VEE Ground Negative power supply (ground)

17 SDO1 O, LVDS Serial data output 1 complement

18 SDO1 O, LVDS Serial data output 1 true

l TEXAS INSTRUMENTS

LMH0395

107 8 9

2124 23 22

VEE

SDI

MISO

SPI_EN

1211

14 SDO0

1920

SCK

VEE

SDI

VEE

AEC+

AEC-

SDO1_DISABLE

MUTEREF

VEE

SDO0

VEE

SDO1

VCC

VEE

DAP = VEE

MOSI

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Pin Functions – Pin Mode (Non-SPI) / SPI_EN = GND(1) (continued)

PIN TYPE DESCRIPTION

NO. NAME

19 AUTO SLEEP I, LVCMOS

Auto Sleep

AUTO SLEEP has precedence over MUTE and BYPASS. This pin has an internal pullup.

H = When no input signal is detected, the device will power down and the outputs will be

in a high impedance state.

L = Device will not enter auto power down.

20 VCC Power Positive power supply (+2.5 V)

21 MUTE I, LVCMOS

Output mute

CD may be tied to this pin to inhibit the output when no input signal is present. MUTE has

precedence over BYPASS. This pin has an internal pulldown.

H = Outputs are forced to a constant logic high state.

L = Outputs are enabled.

22 CD O, LVCMOS Carrier detect

H = No input signal detected.

L = Input signal detected.

23 VEE Ground Negative power supply (ground)

24 VCC Power Positive power supply (+2.5 V)

DAP VEE Ground Connect exposed DAP to negative power supply (ground). See Figure 22 for layout

example

(1) The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.

RTW Package

24-Pin WQFN SPI Mode

Top View

Pin Functions – SPI Mode / SPI_EN = VCC(1)

PIN I/O, TYPE DESCRIPTION

NO. NAME

1 VEE Ground Negative power supply (ground)

2 VEE Ground Negative power supply (ground)

3 SDI I, Analog Serial data true input

4 SDI I, Analog Serial data complement input

5 VEE Ground Negative power supply (ground)

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Pin Functions – SPI Mode / SPI_EN = VCC(1) (continued)

PIN I/O, TYPE DESCRIPTION

NO. NAME

6 SPI_EN I, LVCMOS

SPI register access enable

This pin has an internal pulldown.

H = SPI register access mode

L = Pin mode

7 SDO1_DISABLE I, LVCMOS

Output driver 1 (SDO1, SDO1) disable

This pin has an internal pullup

H (or no connection) = Output driver 1 is in a high-impedance state.

L = Output driver 1 is enabled.

8 AEC+ I/O, Analog AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional)

9 AEC- I/O, Analog AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional)

10 CD O, LVCMOS Carrier detect

H = No input signal detected.

L = Input signal detected.

11 MUTEREF I, Analog Mute reference input that sets the threshold for CD and determines the maximum cable to

be equalized before muting. MUTEREF may be either unconnected or connected to ground

for normal CD operation. There is no MUTE in SPI Mode

12 VEE Ground Negative power supply (ground)

13 SS (SPI) I, LVCMOS SPI slave select

This pin has an internal pullup.

14 SDO0 O, LVDS Serial data output 0 complement

15 SDO0 O, LVDS Serial data output 0 true

16 VEE Ground Negative power supply (ground)

17 SDO1 O, LVDS Serial data output 1 complement

18 SDO1 O, LVDS Serial data output 1 true

19 MISO (SPI) O, LVCMOS SPI Master Input / Slave Output

LMH0395 control data transmit

20 VCC Power Positive power supply (+2.5 V)

21 SCK (SPI) I, LVCMOS SPI serial clock input

22 MOSI (SPI) I, LVCMOS SPI Master Output / Slave Input

LMH0395 control data receive

This pin has an internal pulldown.

23 VEE Ground Negative power supply (ground)

24 VCC Power Positive power supply (+2.5 V)

DAP VEE Ground Connect exposed DAP to negative power supply (ground). See Figure 22 for layout

example.

l TEXAS INSTRUMENTS

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply voltage 3.1 V

Input voltage (all inputs) -0.3 VCC+0.3 V

Junction temperature +125 °C

Storage temperature, Tstg -65 +150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±6000 V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±2000 V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC – VEE Supply voltage 2.375 2.5 2.625 V

Input coupling capacitance 1 µF

TAOperating free-air temperature -40 25 +85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1)

LMH0395

UNITRTW (WQFN)

24 PINS

RθJA Junction-to-ambient thermal resistance 40 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 6 °C/W

(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated

referenced to VEE = 0 Volts.

(2) Typical values are stated for VCC = +2.5 V and TA = +25°C.

(3) The LMH0395 can be optimized for different launch amplitudes through the SPI.

(4) The differential output voltage and offset voltage are adjustable through the SPI.

(5) Typical ICC is measured with a 2.97-Gbps input signal.

(6) The LMH0395 can be optimized for different launch amplitudes through the SPI.

6.5 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted).(1)(2)(3)(4)(5)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH Input voltage high level Logic Inputs 1.7 VCC V

VIL Input voltage low level Logic Inputs VEE 0.7 V

VSDI Input voltage swing 0-m cable length(6) SDI 720 800 880 mVP−P

VCMIN Input common-mode voltage SDI or SDI 1.65 V

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

DC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted).(1)(2)(3)(4)(5)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VSSP-P Differential output voltage, P-P

SDO0, SDO0, SDO1, SDO1 (100-Ω

load), default register settings (4) ,

Figure 1

500 700 900 mVP-P

VOD Differential output voltage 250 350 450 mV

ΔVOD Change in magnitude of VOD for

complementary output states 50 mV

VOS Offset voltage 1.1 1.2 1.35 V

ΔVOS Change in magnitude of VOS for

complementary output states 50 mV

IOS Output short circuit current 30 mA

MUTEREF MUTEREF DC voltage (floating) 1.3 V

MUTERN

GMUTEREF range 0.8 V

VOH Output voltage high level CD, MISO, IOH = –2 mA 2 V

VOL Output voltage low level CD, MISO, IOL = +2 mA 0.2 V

ICC Supply current

Normal operation, dual outputs(5) 55 78 mA

Normal operation, single output(5) 45 65 mA

Power-save mode 7 10 mA

(1) Typical values are stated for VCC = +2.5 V and TA= +25°C.

(2) Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in

accordance with ST RP 184, ST RP 192, and the applicable serial data transmission standard: ST 424, ST 292, or ST 259.

(3) Due to SMPTE naming convention, all SMPTE Engineering Documents will be numbered as a two-letter prefix and a number.

Documents and references with the same root number and year are functionally identical; for example ST 424-2006 and SMPTE 424M-

2006 refer to the same document.

(4) Specification is ensured by characterization.

6.6 AC Electrical Characteristics

over supply voltage and operating temperature ranges, unless otherwise specified(1).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BRMIN Minimum input data rate (SDI, SDI) 125 Mbps

BRMAX Maximum input data rate (SDI,

SDI) 2970 Mbps

TJRAW Jitter for various cable lengths

2.97 Gbps, Belden 1694A,

0-100 meters(2)(3) 0.2 UI

2.97 Gbps, Belden 1694A, 100-

140 meters(2)(3) 0.3 UI

2.97 Gbps, Belden 1694A, 140-

180 meters(2)(3) 0.5 UI

2.97 Gbps, Belden 1694A, 180-

200 meters 0.55 UI

1.485 Gbps, Belden 1694A, 0-

200 meters(2)(3) 0.2 UI

1.485 Gbps, Belden 1694A, 200-

220 meters 0.3 UI

270 Mbps, Belden 1694A,

0-400 meters(2)(3) 0.3 UI

tr, tfOutput rise time, fall time (SDO0,

SDO0, SDO1, SDO1) 20% – 80%, 100-Ωload,

Figure 1(4) 90 130 ps

ΔTR-F Mismatch in rise/fall time (SDO0,

SDO0, SDO1, SDO1) SDO0, SDO0, SDO1,

SDO1See(4)

2 15 ps

tOS Output overshoot (SDO0, SDO0,

SDO1, SDO1) 1% 5%

20%

80%

VOD-

VOD+

VOS

VSSP-P = (VOD+) ± (VOD-)

0V differential

+ VOD

20%

80%

VSSP-P

- VOD

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

AC Electrical Characteristics (continued)

over supply voltage and operating temperature ranges, unless otherwise specified(1).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(5) Input return loss is dependent on board design. The LMH0395 exceeds this specification on the SD395EVK evaluation board with a

return loss network consisting of a 5.6-nH inductor in parallel with a 75-Ωseries resistor on the input.

RLIN Input return loss (SDI, SDI) 5 MHz - 1.5 GHz(5) 15 dB

1.5 GHz - 3.0 GHz(5) 10 dB

RIN Input resistance (SDI, SDI,) Single-ended 1.5 kΩ

CIN Input capacitance (SDI, SDI) Single-ended 0.7 pF

(1) Typical values are stated for VCC = +2.5 V and TA= +25°C.

6.7 Switching Characteristics for SPI Interface

over supply voltage and operating temperature ranges, unless otherwise specified (1).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tODZ MISO driven-to-tristate time

MISO, see Figure 3

20 ns

tOZD MISO tristate-to-driven time 10 ns

tOD MISO output delay time 15 ns

(1) Typical values are stated for VCC = +2.5 V and TA= +25°C.

6.8 Timing Requirements for SPI Interface

over supply voltage and operating temperature ranges, unless otherwise specified (1).

TEST CONDITIONS MIN NOM MAX UNIT

fSCK Frequency SCK 20 MHz

tPH SCK pulse width high

SCK, see Figure 2,Figure 3

40 % SCK

period

tPL SCK pulse width low 40 % SCK

period

tSU MOSI set-up time MOSI, see Figure 2,Figure 3 4 ns

tHMOSI hold time 4 ns

tSSSU SS set-up time

SS, see Figure 2,Figure 3

14 ns

tSSH SS hold time 4 ns

tSSOF SS OFF-time 1 SCK

period

Figure 1. LVDS Output Voltage, Offset, and Timing Parameters

‘5‘ TEXAS INSTRUMENTS 52k ’ ﬁn... ,‘ _

A6 A5 A4 A3 A2 A1 A01

tSSH tSSOF

(host)

SCK

(host)

MOSI

(host)

MISO

(device)

Hi-Z

tSSSU

tSU tH

tPH tPL

tOD

A6 A5 A4 A3 A2 A11 A0 D7 D6 D5 D4 D2 D1 D0D3

tSSH tSSOF

tSSSU

³8x1´ ³16x1´

'21¶7&$5(

tOZD

tODZ

tOZD

Hi-Z Hi-Z

tODZ

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D00

tSSSU

tSU tH

tPH tPL tSSH tSSOF

(host)

SCK

(host)

MOSI

(host)

MISO

(device) Hi-Z '21¶7&$5(

tOZD tODZ

Hi-Z

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Figure 2. SPI Write

Figure 3. SPI Read

I TFJms INSTRUMENTS

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

6.9 Typical Characteristics

Figure 4. Differential Serial Data Output After Equalizing 2

Meters of Belden 1694A at 2.97 Gbps, PRBS10 Figure 5. Differential Serial Data Output After Equalizing 170

Meters of Belden 1694A at 2.97 Gbps, PRBS10

l TEXAS INSTRUMENTS Duvers

AEC+

Equalizer

Filter

AEC-

MUTE

MUTEREF

Restoration/

Level Control

Automatic

Equalization

Control

SDI

SDO0

BYPASS

Output

Drivers

MUTEREF

Energy

Detect Energy

Detect

AUTO SLEEP

Carrier

Detect

SPI_EN

SPI Control

De-Emphasis

Control

SDO1

SDO1_

DISABLE

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

7 Detailed Description

7.1 Overview

The LMH0395 is a 3-Gbps HD/SD SDI low power extended reach adaptive cable equalizer. It is designed to

equalize data transmitted over cable or any media with similar dispersive loss characteristics.. The equalizer

operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST

259, and DVB-ASI standards. The LMH0395 provides extended cable reach with improved immunity to crosstalk

and ultra-low power consumption. The LMH0395 equalizer features active sensing features and design

enhancements including longer cable equalization, lower output jitter, configurable pin mode and SPI modes, a

power-saving sleep mode, and programmable output common-mode voltage and swing. The LMH0395

implements DC restoration to correctly handle pathological data conditions.

The LMH0395 includes power management to further reduce power consumption when no input signal is

present. The output driver offers programmable de-emphasis for up to 40” of FR4 trace losses.

7.2 Functional Block Diagram

The LMH0395 supports two modes of operation. In pin mode, the LMH0395 operates with control pins to set its

operating state. In SPI mode, an optional SPI serial interface can be used to access and configure multiple

LMH0395 devices in a daisy-chain configuration.

This allows users to program the output common-mode voltage and swing, output de-emphasis level, input

launch amplitude, and power management settings. Users may also access a cable length indicator and all pin

mode features.

7.3 Feature Description

The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.

The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This

block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this

function is disabled.

The signals before and after the DC Restoration / Level Control block are used to generate the Automatic

Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter.

The Carrier Detect block generates the carrier detect signal based on the SDI input and an adjustment from the

Mute Reference block.

l TEXAS INSTRUMENTS

0 50 100 150 200 250 300 350 400

1.2

1.4

1.6

1.8

2.0

2.2

MUTEREF(V)

BELDEN 1694A CABLE LENGTH (m)

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Feature Description (continued)

The SPI Control block uses the MOSI, MISO, SCK, and SS signals in SPI mode to control the SPI registers.

SPI_EN selects between SPI mode and pin mode. Driving SPI_EN low enables pin mode.

The Output Drivers produce SDO0, SDO0, SDO1, and SDO1.

7.3.1 Mute Reference (MuteREF)

The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to

equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the

length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically 1.3

V) in order to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable that

can be equalized before carrier detect is de-asserted and the outputs are muted is decreased. MUTEREF may be

left unconnected or connected to ground for normal CD operation. Optionally, the LMH0395 allows the mute

reference to be set digitally through SPI register 03h.

Figure 6 shows the minimum MUTEREF input voltage required to force carrier detect to inactive vs. Belden 1694A

cable length. The results shown are valid for Belden 1694A cable lengths of 0-200 m at 2.97 Gbps, 0-220 m at

1.485 Gbps, and 0-400 m at 270 Mbps.

Figure 6. MuteREF vs. Belden 1694a Cable Length

7.3.2 Carrier Detect (CD) and Mute

Carrier detect CD indicates if a valid signal is present at the LMH0395 input. This signal is a logical OR operation

of internal energy detector and MUTEREF setting (if used). Internal energy detector detects energy across

different data rates. If MUTEREF is used, the carrier detect threshold will be altered accordingly. CD provides a

high voltage when no signal is present at the LMH0395 input. CD is low when a valid input signal is detected.

MUTE can be used to manually mute or enable the output drivers. Applying a high input to MUTE will mute the

LMH0395 outputs by forcing the output to a logic 1. Applying a low input will force the outputs to be active.

In pin mode, CD and MUTE may be tied together to automatically mute the output when no input signal is

present.

7.3.3 Input Interfacing

The LMH0395 accepts single-ended input. The input must be AC coupled. The Functional Block Diagram

diagram shows the typical configuration for a single-ended input. The unused input must be properly terminated

as shown in Figure 7 or Figure 8.

The LMH0395 can be optimized for different launch amplitudes through the SPI (see Launch Amplitude

Optimization in the SPI Register Access section).

The LMH0395 correctly handles equalizer pathological signals for standard definition and high definition serial

digital video, as described in ST RP 178 and RP 198, respectively.

l TEXAS INSTRUMENTS

SDO0

SDI

LMH0395

Coaxial Cable

75:

49.9:

75:

5.6 nH 1.0 PF

1.0 PF

SDI

SDI LMH0346

3G/HD/SD

SDI Reclocker

100: Differential T-Line 100:

SDO1

SDI

LMH0346

3G/HD/SD

SDI Reclocker

100: Differential T-Line 100:

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Feature Description (continued)

7.3.4 Output Interfacing

The LMH0395 dual output differential pairs, SDO0, SDO0, SDO1, and SDO1 are internally terminated 100-Ω

LVDS outputs. These outputs can be DC coupled to most common differential receivers.

The default output common-mode voltage (VOS) is 1.2 V. The output common-mode voltage may be adjusted

through the SPI in 200 mV increments, from 0.8 V to 1.2 V (see Output Driver Adjustments and De-Emphasis

Setting in the SPI Register Access section). When the output common mode is supply referenced, the common-

mode voltage is about 1.35 V (for 700 mVP-P differential swing). This adjustable output common-mode voltage

offers flexibility for interfacing to many types of receivers.

The default differential output swing (VSSP-P) is 700 mVP-P. The differential output swing may be adjusted through

the SPI. Valid options are 400, 600, 700, or 800 mVP-P (see Output Driver Adjustments and De-Emphasis Setting

in the SPI Register Access section).

The LMH0395 output should be DC coupled to the input of the receiving device where possible. 100-Ω

differential transmission lines should be used to connect between the LMH0395 outputs and the input of the

receiving device.

The LMH0395 output should not be DC coupled to CML inputs. If there are strong pull-up resistors (that is, 50 Ω)

at the receiving device, AC coupling should be used. The value of these AC-coupling capacitors should be large

enough (typically 4.7 µF) to accommodate for the SD pathological video pattern.

Figure 7 shows an example of a DC-coupled interface between the LMH0395 and LMH0346 SDI reclocker. The

differential transmission line should be terminated with a 100-Ωresistor at the receiving device as shown. The

resistor should be placed as close as possible to the LMH0346 input. If desired, this network may be terminated

with two 50-Ωresistors and a center-tap capacitor to ground in place of the single 100-Ωresistor.

Figure 8 shows an example of a DC-coupled interface between the LMH0395 and LMH0356 SDI reclocker. The

LMH0356 inputs have internal 50-Ωterminations (100 Ωdifferential) to terminate the transmission line, so no

additional components are required.

The LMH0395 output drivers are equipped with programmable output de-emphasis to minimize inter-symbol

interference caused by the loss dispersion from driving signals across PCB traces (see Output Driver

Adjustments and De-Emphasis Setting in the SPI Register Access section). De-emphasis works with all

combinations of output common-mode voltage and output voltage swing settings to support DC coupling to the

receiving device.

Figure 7. DC Output Interface To LMH0346 Reclocker

l TEXAS INSTRUMENTS

SDO0

SDI0

LMH0395

Coaxial Cable

75:

49.9:

75:

5.6 nH 1.0 PF

1.0 PF

SDI

SDI LMH0356

3G/HD/SD

SDI Reclocker

100: Differential T-Line

SDO1

SDI0

LMH0356

3G/HD/SD

SDI Reclocker

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Feature Description (continued)

Figure 8. DC Output Interface To LMH0356 Reclocker

7.4 Device Functional Modes

The LMH0395 supports two modes of operation. In pin mode, the LMH0395 operates with control pins to set its

operating state. In SPI mode, an optional SPI serial interface can be used to access and configure multiple

LMH0395 devices in a daisy-chain configuration.

This allows users to program the output common-mode voltage and swing, output de-emphasis level, input

launch amplitude, and power management settings. Users may also access a cable length indicator and all pin

mode features.

7.4.1 Auto Sleep

The auto sleep mode allows the LMH0395 to power down when no input signal is detected. If the AUTO SLEEP

pin is set high, the LMH0395 goes into a deep power-save mode when no signal is detected. The device powers

on again once an input signal is detected. If the AUTO SLEEP pin is set low, the LMH0395 will always be on and

will not enter power-save mode. The auto sleep functionality can be turned off by setting AUTO SLEEP low or

tying this pin to ground. An additional auto sleep setting available in SPI mode can be used to force the equalizer

to power down regardless of whether there is an input signal or not. Auto sleep has precedence over mute and

bypass modes.

In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs

and should not have any impact on the system timing requirements. The device will wake up automatically once

an input signal is detected, and the delay between signal detection and full functionality of the equalizer is

negligible (about 5 ms). The overall system will be limited only by the settling time constant of the equalizer

adaptation loop.

7.5 Programming

7.5.1 SPI Register Access

Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0395 provides

programmable output common-mode voltage and swing, digital MUTEREF, and launch amplitude optimization.

There are eight supported 8-bit registers in the device (see Table 1). The LMH0395 supports SPI daisy-chaining

among an unlimited number of LMH0395 devices.

7.5.1.1 SPI Transaction Overview

Each SPI transaction to a single device is 16-bits long. The transaction is initiated by driving SS low, and

completed by returning SS high. The 16-bit MOSI payload consists of the read/write command (“1” for reads and

“0” for writes), the seven address bits of the device register (MSB first), and the eight data bits (MSB first). The

LMH0395 MOSI input data is latched on the rising edge of SCK, and the MISO output data is sourced on the

falling edge of SCK.

l TEXAS INSTRUMENTS

Host

MISO

MOSI

SCK

LMH0395

MOSI MISO

SCK

LMH0395

MOSI MISO

SCK

LMH0395

MOSI MISO

SCK

LMH0395

MOSI MISO

Device 1 Device 2 Device 3 Device N

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Programming (continued)

In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO

output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO

output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data

(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.

7.5.1.2 SPI Write

The SPI write is shown in Figure 2. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write

command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the

LMH0395's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data

shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 2.

7.5.1.3 SPI Read

The SPI read is shown in Figure 3. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed

by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload

consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI

payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the

MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0395's MOSI input. The prior

SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are

typically ignored (this is shown as “Don't Care” on the MISO output in Figure 3. SS must return high and then is

driven low again before the second 16 bits (all “1”s) are sent to the LMH0395's MOSI input. Once again, the prior

SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested

read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read

transaction, as shown by D7-D0 in Figure 3.

7.5.1.4 SPI Daisy-Chain Operation

The LMH0395 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0395

devices. Each LMH0395 device is directly connected to the SCK and SS pins on the host. However, only the first

LMH0395 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is

connected to the host’s MISO pin. The MISO pin of each intermediate LMH0395 device in the chain is connected

to the MOSI pin of the next LMH0395 device, creating a serial shift register. This daisy-chain architecture is

shown in Figure 9.

Figure 9. SPI Daisy Chain System Architecture

In a daisy-chain configuration of N LMH0395 devices, the host conceptually sees a shift register of length 16xN.

Therefore the length of SPI transactions (as previously described) is 16xN bits, and SS must be asserted for

16xN clock cycles for each SPI transaction.

l TEXAS INSTRUMENTS ,_\ 1. f _( X D kkkkk mix Xi'umw ) __________ )_ \ \ \ 4 x x . x > ---------- r 4 x x ' x > ---------- k EDIIIIN ﬁ'ﬁ r\ f

(host)

SCK

(host) 16xN clocks

Device N-1

Read Data Device 1

Read Data

Device N

Read Data

MOSI

(host)

'21¶7&$5(

SPI Read Data

16xN clocks

³16x1´ ³16x1´ ³16x1´

Device N

Read Data Device N-1

Read Data Device 1

Read Data

SPI Read Data

MISO

(host)

A6 A5 A4 A3 A2 A1 A01 ³8x1´

A6 A5 A4 A3 A2 A11 A0 D7 D6 D5 D4 D2 D1 D0D3

(host)

SCK

(host) 16xN clocks

Device N-1

Write Data Device N-2

Write Data Device N-3

Write Data

Device N

Write Data

MOSI (host)

MOSI Device 1

MISO Device 1

MOSI Device 2 '21¶7&$5(

Device 1

Write Data

Device N

Write Data Device N-1

Write Data Device N-2

Write Data Device 2

Write Data

'21¶7&$5( '21¶7&$5( '21¶7&$5( '21¶7&$5( Device N

Write Data

MISO Device N-1

MOSI Device N

SPI Write Data

A6 A5 A4 A3 A2 A10 A0 D7 D6 D5 D4 D2 D1 D0D3

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Programming (continued)

7.5.1.5 SPI Daisy-Chain Write

Figure 10 shows the SPI daisy-chain write for a daisy-chain of N devices. The SS signal is driven low and SCK is

toggled for 16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit

SPI write data for Device N (the last device in the chain), followed by the write data for Device –1, Device –2,

and so forth, ending with the write data for Device 1 (the first device in the chain). The 16-bit SPI write data for

each device consists of a “0” (write command), seven address bits, and eight data bits. After the SPI daisy-chain

write, SS must return high and then the write occurs for all devices in the daisy-chain.

Figure 10. SPI Daisy-Chain Write

7.5.1.6 SPI Daisy-Chain Read

Figure 11 shows the SPI daisy-chain read for a daisy-chain of N devices. The SPI daisy-chain read is 32xN bits

long, consisting of 16xN bits for the read transaction followed by 16xN bits for the dummy read transaction (all

“1”s) to shift out the read data on the MISO output. The SS signal is driven low and SCK is toggled for 16xN

clocks. The first 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit SPI read data

for Device N (the last device in the chain), followed by the read data for Device –1, Device –2, and so forth,

ending with the read data for Device 1 (the first device in the chain). The 16-bit SPI read data for each device

consists of a “1” (read command), seven address bits, and eight “1”s (which are ignored). After the first 16xN bit

transaction, SS must return high (to latch the data) and then is driven low again before the second 16xN bit

transaction of all “1”s is sent to the MOSI input. The requested read data is shifted out on MISO starting with the

data for Device N and ending with the data for Device 1. After this transaction, SS must return high.

Figure 11. SPI Daisy-Chain Read

l TEXAS INSTRUMENTS %

0x7F 0x5A1

MOSI

(host)

R/W Addr Data

0x7F 0x5A1

R/W Addr Data

0x7F 0x5A1

R/W Addr Data

XXX XX XXX XX XXX

MISO

(host) XX

0x7F 0x5A1

R/W Addr Data

0x7F1 0x5A

0x01 0x220

MOSI

(host)

R/W Addr Data

(Device 3)

0x00 0xFF1

R/W Addr Data

(Device 2)

0x00 0x100

R/W Addr Data

(Device 1)

XXX XX XXX XX XXX

MISO

(host)

0x7F 0xFF1

R/W Addr Data

(Device 3)

0x7F 0xFF1

R/W Addr Data

(Device 2)

0x7F 0xFF1

R/W Addr Data

(Device 1)

0x01 0x220 0x00 0x881 0x00 0x100

48-bit SPI Transaction #1 48-bit SPI Transaction #2

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Programming (continued)

7.5.1.7 SPI Daisy-Chain Read and Write Example

The following example further clarifies LMH0395 SPI daisy-chain operation. Assume a daisy-chain of three

LMH0395 devices (Device 1, Device 2, and Device 3), with Device 1 as the first device in the chain and Device 3

as the last device in the chain, as shown by the first three devices in Figure 9. Because there are three devices

in the daisy-chain, each SPI transaction is 48-bits long.

This example shows an SPI operation combining SPI reads and writes in order to accomplish the following three

tasks:

1. Write 0x22 to register 0x01 of Device 3 in order to set the output swing of output driver 0 to 400 mVP-P.

2. Read the contents of register 0x00 of Device 2.

3. Write 0x10 to register 0x00 of Device 1 in order to force the sleep mode.

Figure 12 shows the two 48-bit SPI transactions required to complete these tasks (the bits are shifted in left to

right).

Figure 12. SPI Daisy-Chain Read and Write Example

The following occurs at the end of the first transaction:

1. Write 0x22 to register 0x01 of Device 3.

2. Latch the data from register 0x00 of Device 2.

3. Write 0x10 to register 0x00 of Device 1.

In the second transaction, three dummy reads (each consisting of 16 “1”s) are shifted in, and the read data from

Device 2 (with value 0x88) appears on MISO in the 25th through 32nd clock cycles.

7.5.1.8 SPI Daisy-Chain Length Detection

A useful operation for the host may be to detect the length of the daisy-chain. This is a simple matter of shifting

in a series of dummy reads with a known data value (such as 0x5A). For an SPI daisy-chain of N LMH0395

devices, the known data value will appear on the host's MISO pin after N+1 writes. Assuming a daisy-chain of

three LMH0395 devices, the result of this operation is shown in Figure 13.

Figure 13. SPI Daisy-Chain Length Detection

7.5.1.9 Output Driver Adjustments and De-Emphasis Setting

The output driver swing (amplitude), offset voltage (common-mode voltage), and de-emphasis level are

adjustable through SPI register 01h. The output driver to control with SPI register 01h (either output driver 0 or

output driver 1) can be selected through bit 2 of SPI register 00h.

The output swing is adjustable through bits [7:6] of SPI register 01h. The default value for these register bits is

10b for a peak to peak differential output voltage of 700 mVP-P. The output swing can be set for 400 mVP-P, 600

mVP-P , 700 mVP-P, or 800 mVP-P.

l TEXAS INSTRUMENTS

0 50 100 150 200 250 300 350 400

100

125

150

175

200

225

250

CLI (decimal value)

BELDEN 1694A CABLE LENGTH (m)

3G/HD

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Programming (continued)

The offset voltage is adjustable through bits [5:4] of SPI register 01h. The default value for these register bits is

“10b” for an output offset of 1.2 V. The output common-mode voltage may be adjusted in 200 mV increments,

from 0.8 V to 1.2 V. It can be set to “11b” for the maximum offset voltage. At this maximum offset voltage setting,

the outputs are referenced to the positive supply and the offset voltage is around 1.35 V.

The output de-emphasis is turned on or off by bit 3 of SPI register 01h, and the de-emphasis level is set by bits

[2:1] of SPI register 01h. The output de-emphasis level may be set for 0 dB (for driving up to 10” FR4), -3 dB (for

driving 10-20” FR4), -5 dB (for driving 20-30” FR4), or -7 dB (for driving 30-40” FR4).

7.5.1.10 Launch Amplitude Optimization

The LMH0395 can compensate for attenuation of the input signal prior to the equalizer. This compensation is

useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and

is controlled by SPI register 02h.

Bit 7 of SPI register 02h is used for the launch amplitude setting. At the default setting of “0”, the LMH0395

operates normally and expects a launch amplitude of 800 mVP-P. Bit 7 may be set to “1” to optimize the LMH0395

for input signals with 6 dB of attenuation (400 mVP-P).

7.5.1.11 Cable Length Indicator (CLI)

The cable length indicator (CLI) provides an indication of the length of the cable attached to input. CLI is

accessible through bits [7:0] of SPI register 06h. The 8-bit setting ranges in decimal value from 0 to 247

(“00000000” to “11110111” binary), corresponding to 0 to 400m of Belden 1694A cable. For 3G and HD input,

CLI is 1.25m per step. For SD input, CLI is 1.25m per step, less 20m, from 0 to 191 decimal, and 3.5m per step

from 192 to 247 decimal.

To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for 3G or HD input:

Cable Length = CLI x 1.25 (1)

To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for SD input:

FOR CLI ≤191,

Cable Length = (CLI x 1.25) - 20 (2)

For CLI > 191,

Cable Length = ((191 x 1.25) - 20) + ((CLI - 191) x 3.5) (3)

Figure 14 shows typical CLI values vs. Belden 1694A cable length. CLI is valid for Belden 1694A cable lengths of

0-200 m at 2.97 Gbps, 0-220 m at 1.485 Gbps, and 0-400 m at 270 Mbps. Note: Given the continuous adaptive

nature of the equalizer, the CLI values may vary constantly within several steps.

Figure 14. CLI vs. Belden 1694a Cable Length

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

7.6 Register Maps

Table 1. SPI Registers

Address R/W Name Bits Field Default Description

00h R/W General Control

7 Carrier Detect Read only.

0: No carrier detected.

1: Carrier detected.

6 Mute 0

Mute has precedence over

Bypass.

0: Normal operation.

1: Outputs muted.

5 Bypass 0 0: Normal operation.

1: Equalizer bypassed.

4:3 Sleep Mode 01

Sleep mode control. Sleep has

precedence over Mute and

Bypass.

00: Disable sleep mode (force

equalizer to stay enabled).

01: Sleep mode active when no

input signal detected.

10: Force equalizer into sleep

mode (powered down)

regardless of whether there is

an input signal or not.

11: Reserved.

2 Driver Select 0

Select output driver for

control/status.

0: Register 01h bits [7:1] control

output driver 0 (SDO0, SDO0)

1: Register 01h bits [7:1] control

output driver 1 (SDO1, SDO1)

1 Master Reset 0

Reset registers and state

machine. (This bit is self-

clearing.)

0: Normal operation.

1: Reset registers and state

machine.

0 Acquisition Reset 0

Reset state machine. (This bit is

self-clearing.)

0: Normal operation.

1: Reset state machine.

01h R/W Output Driver

7:6 Output Swing 10

Output driver swing (VSSP-P).

00: VSSP-P = 400 mVP-P.

01: VSSP-P = 600 mVP-P.

10: VSSP-P = 700 mVP-P.

11: VSSP-P = 800 mVP-P.

5:4 Offset Voltage 10

Output driver offset voltage

(common-mode voltage).

00: VOS = 0.8 V.

01: VOS = 1.0 V.

10: VOS = 1.2 V.

11: VOS referenced to positive

supply.

3 De-Emphasis 0

Output driver de-emphasis

control.

0: De-emphasis disabled.

1: De-emphasis enabled.

2:1 De-Emphasis Amplitude

Level 01

Output driver de-emphasis

level.

00: 0 dB (no de-emphasis).

01: -3 dB de-emphasis.

10: -5 dB de-emphasis.

11: -7 dB de-emphasis.

0 Reserved 0 Reserved (read only).

l TEXAS INSTRUMENTS

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

Table 1. SPI Registers (continued)

Address R/W Name Bits Field Default Description

02h R/W Launch Amplitude

Control

7 Launch Amplitude Control 0

Launch amplitude optimization

setting.

0: Normal optimization with no

external attenuation (800 mVP-P

launch amplitude).

1: Optimized for 6 dB external

attenuation (400 mVP-P launch

amplitude).

6:0 Reserved 1101000 Reserved as 1101000. Always

write 1101000 to these bits.

03h R/W MUTEREF

7 Driver 1 Disable 0

SDO1_DISABLE pin has

precedence over this register

setting; must set

SDO1_DISABLE pin low first to

allow control of Driver 1 Disable

through this register bit.

0: Output driver 1 (SDO1,

SDO1) enabled.

1: Output driver 1 (SDO1,

SDO1) disabled.

6 Driver 0 Disable 0

0: Output driver 0 (SDO0,

SDO0) enabled.

1: Output driver 0 (SDO0,

SDO0) disabled.

5 MUTEREF Mode 0 0: Use MUTEREF pin.

1: Use digital MUTEREF.

4:0 Digital MUTEREF Setting 11111

Digital MUTEREF (10m per

step).

00000: Mute when cable (EQ

boost) ≥10 m.

......

01111: Mute when cable (EQ

boost) ≥160 m.

......

11111: Never mute.

04h R Device ID

7:6 Reserved 00 Reserved.

5:4 EQ ID 10

00: LMH0384 device.

01: LMH0394 device.

10: LMH0395 device.

11: Reserved.

3:0 Die Revision 0011 Die revision.

05h R Rate Indicator

7:6 Reserved 00 Reserved.

5 Rate Indicator 0: SD.

1: 3G/HD.

4:0 Reserved 11000 Reserved.

06h R Cable Length Indicator 7:0 Cable Length Indicator

Cable Length Indicator (CLI),

with 10% accuracy.

00000000: Short cable.

......

11110111: Maximum cable.

11111000: Reserved.

......

11111111: Reserved.

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

Table 1. SPI Registers (continued)

Address R/W Name Bits Field Default Description

07h R Launch Amplitude

Indication

7:2 Launch Amplitude

Indication

Indication of launch amplitude:

1% or 0.08 dB per step with 5%

accuracy.

000000: Nominal -32%.

......

011111: Nominal -1%.

100000: Nominal.

100001: Nominal +1%.

......

111111: Nominal +31%.

1:0 Reserved Reserved.

l TEXAS INSTRUMENTS .H’Wj 'U’Wj ”WE

9.76 k:

3.16 k:

MOSI

SCK

3.16 k:

LMH0395

3.3V

Compliant

SPI Host 9.76 k:

9.76 k:

MISO

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMH0395 3 Gbps HD/SD Dual Output SDI Low Power Extended Reach Adaptive Cable Equalizer is

designed to equalize data transmitted over cable (or any media with similar dispersive loss characteristics). The

equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292,

ST 344, ST 259, and DVB-ASI standards. Additional features include separate carrier detect and output mute

pins which may be tied together to mute the output when no signal is present. A programmable mute reference is

provided to mute the output at a selectable level of signal degradation. The bypass pin allows the adaptive

equalizer to be bypassed. The LMH0395 accepts single-ended input. The input must be AC coupled. The

LMH0395 correctly handles equalizer pathological signals for standard definition and high definition serial digital

video, as described in ST RP 178 and RP 198, respectively.

8.1.1 Interfacing to 3.3-V SPI

The LMH0395 may be controlled through optional SPI register access. The LMH0395 SPI pins support 2.5-V

LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be

taken when interfacing the SPI pins to other voltage levels.

The 2.5-V LMH0395 SPI pins may be interfaced to a 3.3-V compliant SPI host by using a voltage divider or level

translator. One implementation is a simple resistive voltage divider as shown in Figure 15.

Figure 15. 3.3-V SPI Interfacing

8.1.2 Crosstalk Immunity

Single-ended SDI signals are susceptible to crosstalk and good design practices should be employed to

minimize its effects. Most crosstalk originates through capacitive coupling from adjacent signals routed closely

together through traces and connectors. To reduce capacitive coupling, SDI signals should be appropriately

spaced apart or insulated from one another. This can be accomplished by physically isolating signal traces in the

layout and by providing additional ground pins between signal traces in connectors as necessary. These

techniques help to reduce crosstalk but do not eliminate it.

The LMH0395 was designed specifically with crosstalk in mind and incorporates advanced circuit design

techniques that help to isolate and minimize the effects of cross-coupling in high-density system designs.The

LMH0395's enhanced design results in minimal degradation in cable reach in the presence of crosstalk and

overall superior immunity against cross-coupling from neighboring channels.

l TEXAS INSTRUMENTS ||"”||

VCC

LMH0395

VEE

SDI

SDO1

DAP

613

11 20

SPI_EN

SDO1

MISO

AEC+

AEC- MOSI

VCC

SCK

Coaxial Cable

75:

49.9:

75:

5.6 nH 1.0 PF

1.0 PF

VCC

0.1 PF

Differential

Outputs

VCC

0.1 PF

MUTEREF

(SPI) SS

(SPI) MOSI

(SPI) SCK

(SPI) MISO

SDO0 14

SDO0

7SDO1_

DISABLE

VEE

SDO1_DISABLE

MUTEREF

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

8.2 Typical Application

Figure 16 shows the application circuit for the LMH0395 in SPI mode. (Note: The application circuit shows an

external capacitor connected between the AEC+ and AEC- pins as commonly configured in legacy equalizers.

This capacitor is optional and not necessary for the LMH0395; the AEC+ and AEC- pins may be left unconnected

with no change in performance.)

Figure 16. Application Circuit (SPI Mode)

8.2.1 Design Requirements

Table 2 lists the design parameters of the LMH0395.

Table 2. LMH0395 Design Parameters

DESIGN PARAMETERS REQUIREMENTS

Input AC coupling capacitors Required. A common type of AC coupling capacitor

is 1 µF ± 10% X7R ceramic capacitor (0402 or

0201 size).

Distance from Device to BNC Keep this distance as short as possible to minimize

parasitic

High Speed SDI, and SDI, trace impedance Design single-ended trace impedance with 75 Ω±

High Speed SDO0, SDO0, SDO1, and SDO1 trace

impedance Design differential trace impedance with 100 Ω±

DC Power Supply Coupling Capacitors To minimize power supply noise, use 0.1-µF

capacitors as close to the device VDD pin as

possible

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

1. Maximum power draw for PCB regulator selection: Use maximum current consumption in the data sheet to

compute maximum power consumption.

I TEXAS INSTRUMENTS

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

2. Closely compare schematic against typical connection diagram in the data sheet.

3. Plan out the PCB layout and component placement to minimize parasitic.

4. Consult the BNC vendor for optimum BNC landing pattern.

8.2.3 Application Curves

Figure 17. Differential Serial Data Output After Equalizing

200 Meters of Belden 1694A at 1.485 Gbps, PRBS10 Figure 18. Differential Serial Data Output After Equalizing

200 Meters of Belden 1694A at 270 Mbps, PRBS10

Figure 19. Differential Serial Data Output 2.97 Gbps

PRBS10 After 20” FR4 and 0 dB De-Emphasis Figure 20. Differential Serial Data Output 2.97 Gbps

PRBS10 After 20” FR4 and 5dB De-Emphasis

8.3 Dos and Don'ts

Special attention should be paid to the PCB layout for the high speed signals. SMPTE specifies the requirements

for the Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over coaxial cables.

One of the requirements is meeting the required Return Loss. This requirement specifies how closely the port

resembles 75-Ωimpedance across a specified frequency band. The SMPTE specifications also defines the use

of AC coupling capacitors for transporting uncompressed serial data streams with heavy low frequency content.

This specification requires the use of a 1-µF AC coupling capacitor on the input of the LMH0395 to avoid low

frequency bandwidth limitation.

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

9 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the recommended operating conditions in terms of DC

voltage and maximum current consumption.

2. The maximum current draw for the LMH0395 is provided in the data sheet. This number can be used to

calculate the maximum current the supply must provide.

3. The LMH0395 does not require any special power supply filtering, provided the recommended operating

conditions are met. Use 0.1-µF capacitors as close to the device VDD pin as possible

10 Layout

10.1 Layout Guidelines

For information on layout and soldering of the WQFN package, please refer to the following application note: AN-

1187 Leadless Leadframe Package (LLP),SNOA401.

The ST 424, 292, and 259 standards have stringent requirements for the input return loss of receivers, which

essentially specify how closely the input must resemble a 75-Ωnetwork. Any non-idealities in the network

between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize

impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this

trace is 75-Ω. Please consider the following PCB recommendations:

• Use surface mount components, and use the smallest components available. In addition, use the smallest

size component pads.

• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.

• Select a board stack-up that supports both 75-Ωsingle-ended traces and 100-Ωloosely-coupled differential

traces.

• Place return loss components closest to the equalizer input pins.

• Maintain symmetry on the complementary signals.

• Route 100-Ωtraces uniformly (keep trace widths and trace spacing uniform along the trace).

• Avoid sharp bends in the signal path; use 45° or radial bends.

• Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and

ground pins to the respective power or ground planes.

;/ LE $223 \ \le IIIIII

5 Vias in between 4 quadrant

Of top solder paste

Ground and V relief under return loss

Passive components and pads

LMH0395

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LMH0395

10.2 Layout Examples

Figure 22 and Figure 21 demonstrate the LMH0395EVM PCB layout. Ground and supply relief under the return

loss passive components and pads reduces parasitic - improving return loss performance. The solder mask for

the DAP is divided into four quadrants. Five vias are placed such that they are in the boundary of the 4

quadrants. This is done to ensure vias are not covered by solder mask - improving solerability. This practice

improves both thermal performance and soldering during board assembly.

Figure 21. LMH0395EVM Top Etch Layout Example

Figure 22. LMH0395EVM Top Solder Paste Mask

l TEXAS INSTRUMENTS

LMH0395

www.ti.com

SNLS323N –AUGUST 2010–REVISED JANUARY 2017

Product Folder Links: LMH0395

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Sample: Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH0395SQ/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L0395

LMH0395SQE/NOPB ACTIVE WQFN RTW 24 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L0395

LMH0395SQX/NOPB ACTIVE WQFN RTW 24 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L0395

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH0395SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LMH0395SQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LMH0395SQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Nov-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH0395SQ/NOPB WQFN RTW 24 1000 208.0 191.0 35.0

LMH0395SQE/NOPB WQFN RTW 24 250 208.0 191.0 35.0

LMH0395SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Nov-2021

Pack Materials-Page 2

RTW0024A 02 13/)

www.ti.com

PACKAGE OUTLINE

24X 0.3

0.2

24X 0.5

0.3

0.8 MAX

(0.1) TYP

0.05

0.00

20X 0.5

2.5

2X 2.5

2.6 0.1

A4.1

3.9 B

4.1

3.9

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

613

7 12

24 19

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05 C

EXPOSED

THERMAL PAD

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

24X (0.25)

24X (0.6)

( ) TYP

VIA

0.2

20X (0.5)

(3.8)

(1.05)

( 2.6)

(R )

TYP

0.05

(1.05)

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

SYMM

712

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

RTW0024A

www.ti.com

EXAMPLE STENCIL DESIGN

24X (0.6)

24X (0.25)

20X (0.5)

(3.8)

4X ( 1.15)

(0.675)

TYP

(0.675) TYP

(R ) TYP0.05

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

712

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMH0395 Datasheet by Texas Instruments

INFORMATION

HELP

CONTACT US

FOLLOW US