LT1122 Datasheet by Analog Devices Inc.

L7L|nt “I2 LT1122 TECHNOLOGY L7 LJUW 1
LT1122
1
1122fb
For more information www.linear.com/LT1122
TYPICAL APPLICATION
FEATURES DESCRIPTION
Fast Settling, JFET Input
Operational Amplifier
The LT
®
1122 JFET input operational amplifier combines
high speed and precision performance.
A unique poly-gate JFET process minimizes gate series
resistance and gate-to-drain capacitance, facilitating wide
bandwidth performance, without degrading JFET transis-
tor matching.
It slews at 80V/µs and settles in 340ns. The LT1122 is
internally compensated to be unity-gain stable, yet it has
a bandwidth of 14MHz at a supply current of only 7mA. Its
speed makes the LT1122 an ideal choice for fast settling
12-bit data conversion and acquisition systems.
The LT1122 offset voltage of 120µV, and voltage gain of
500,000 also support the 12-bit accurate applications.
The input bias current of 10pA and offset current of 4pA
combined with its speed allow the LT1122 to be used in
such applications as high speed sample and hold ampli-
fiers, peak detectors, and integrators.
12-Bit Voltage Output D/A Converter Large-Scale Response
APPLICATIONS
n 100% Tested Settling Time 340ns Typ
to 1mV at Sum Node, 10V Step 540ns Max
Tested with Fixed Feedback Capacitor
n Slew Rate 60V/µs Min
n Gain-Bandwidth Product 14MHz
n Power Bandwidth (20VP-P) 1.2 MHz
n Unity-Gain Stable; Phase Margin 60°
n Input Offset Voltage 600µV Max
n Input Bias Current 25°C 75pA Max
70°C 600pA Max
■ Input Offset Current 25°C 40pA Max
70°C 150pA Max
■ Low Distortion
n Fast 12-Bit D/A Output Amplifiers
n High Speed Buffers
n Fast Sample-and-Hold Amplifiers
n High Speed Integrators
n Voltage to Frequency Converters
n Active Filters
n Log Amplifiers
n Peak Detectors
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and C-Load
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
0mA TO 2mA
OR 4mA
2
3
6
CF
V
0V TO 10V
OUT
12-BIT CURRENT OUTPUT D/A CONVERTER
CF = 5pF TO 17pF
(DEPENDING ON D/A CONVERTER USED)
+
–
LT1122
LT1122•TA01
+
200ns/DIV
AV = –1
1122 TA07
5V/DIV
LT1122 u E j K j E :| E :I E :I K j E :| E j OBSOLETE PAEKAGE J8 PACKAGE BVLEAD HERME'HC DIP TJW = Ham. 9“ = 100°C/W 2 L7LJ1‘JW
LT1122
2
1122fb
For more information www.linear.com/LT1122
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...................................................... ± 20V
Differential Input Voltage ....................................... ± 40V
Input Voltage .......................................................... ± 20V
Output Short Circuit Duration .......................... Indefinite
Lead Temperature (Soldering, 10 sec.) ..................300°C
(Note 1)
ORDER INFORMATION
Operating Temperature Range
LT1122AM/BM/CM/DM (OBSOLETE) .. –55°C to 125°C
LT1122AC/BC/CC/DC/CS/DS ................. –40°C to 85°C
Storage Temperature Range
All Devices .......................................... –65°C to 150°C
1
2
3
4
8
7
6
5
TOP VIEW
–IN
+IN
V–
V+
OUT
VOS TRIM
N8 PACKAGE
8-LEAD PDIP
VOS
TRIM
SPEED BOOST/
OVERCOMP
TJMAX = 150°C, θJA = 130°C/W
OBSOLETE PACKAGE
J8 PACKAGE 8-LEAD HERMETIC DIP
TJMAX = 175°C, θJA = 100°C/W
1
2
3
4
8
7
6
5
TOP VIEW
V+
OUT
VOS TRIM
–IN
+IN
V–
S8 PACKAGE
8-LEAD PLASTIC SO
SPEED BOOST/
OVERCOMP
VOS
TRIM
TJMAX = 150°C, θJA = 190°C/W
PIN CONFIGURATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1122ACN8#PBF LT1122ACN8#TRPBF LT1122ACN8 8-Lead Plastic DIP –40°C to 85°C
LT1122BCN8#PBF LT1122BCN8#TRPBF LT1122BCN8 8-Lead Plastic DIP –40°C to 85°C
LT1122CCN8#PBF LT1122CCN8#TRPBF LT1122CCN8 8-Lead Plastic DIP –40°C to 85°C
LT1122DCN8#PBF LT1122DCN8#TRPBF LT1122DCN8 8-Lead Plastic DIP –40°C to 85°C
LT1122CS8#PBF LT1122CS8#TRPBF 1122C 8-Lead Plastic SO –40°C to 85°C
LT1122DS8#PBF LT1122DS8#TRPBF 1122D 8-Lead Plastic SO –40°C to 85°C
OBSOLETE PACKAGE
LT1122AMJ8#PBF LT1122AMJ8#TRPBF LT1122AMJ8 8-Lead Hermetic DIP –55°C to 125°C
LT1122BMJ8#PBF LT1122BMJ8#TRPBF LT1122BMJ8 8-Lead Hermetic DIP –55°C to 125°C
LT1122CMJ8#PBF LT1122CMJ8#TRPBF LT1122CMJ8 8-Lead Hermetic DIP –55°C to 125°C
LT1122DMJ8#PBF LT1122DMJ8#TRPBF LT1122DMJ8 8-Lead Hermetic DIP –55°C to 125°C
LT1122ACJ8#PBF LT1122ACJ8#TRPBF LT1122ACJ8 8-Lead Hermetic DIP –40°C to 85°C
LT1122BCJ8#PBF LT1122BCJ8#TRPBF LT1122BCJ8 8-Lead Hermetic DIP –40°C to 85°C
LT1122CCJ8#PBF LT1122CCJ8#TRPBF LT1122CCJ8 8-Lead Hermetic DIP –40°C to 85°C
LT1122DCJ8#PBF LT1122DCJ8#TRPBF LT1122DCJ8 8-Lead Hermetic DIP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part markings, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LT1122 L7 LJUW 3
LT1122
3
1122fb
For more information www.linear.com/LT1122
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS
LT1122AM/BM
LT1122AC/BC
LT1122CM/DM
LT1122CC/DC
LT1122CS/DS
UNITSMIN TYPMAX MIN TYP MAX
VOS Input Offset Voltage 120 600 130 900 µV
IOS Input Offset Current 4 40 5 50 pA
IBInput Bias Current 10 75 12 100 pA
Input Resistance
Differential
Common Mode
VCM = –10V to 8V
VCM = 8V to 11V
1012
1012
1011
1012
1012
1011
Ω
Ω
Ω
Input Capacitance 4 4 pF
SR Slew Rate AV = – 1 60 80 50 75 V/µs
Settling Time (Note 2) 10V to 0V, – 10V to 0V
100% Tested: A- and C-Grades to 1mV at Sum Node
B- and D-Grades to 1mV at Sum Node
All Grades to 0.5mV at Sum Node
340
350
450
540
350
360
470
590
ns
ns
ns
GBW Gain-Bandwidth Product Power
Bandwidth
VOUT = 20VP-P
14
1.2
13
1.1
MHz
MHz
AVOL Large-Signal Voltage Gain VOUT = ±10V, RL = 2kΩ
VOUT = ±10V, RL = 600Ω
180
130
500
250
150
110
450
220
V/mV
V/mV
CMRR Common-Mode Rejection Ratio VCM = ±10V 83 99 80 98 dB
Input Voltage Range (Note 4) ±10.5 ±11 ±10.5 ±11 V
PSRR Power Supply Rejection Ratio VS = ±10V to ±18V 86 103 82 101 dB
Input Noise Voltage 0.1Hz to 10Hz 3.0 3.3 µVP-P
Input Noise Voltage Density fO = 100Hz
fO = 10kHz
25
14
27
15
nV/√Hz
nV/√Hz
Input Noise Current Density fO = 100Hz, fO = 10kHz 2 2 fA/√Hz
VOUT Output Voltage Swing RL = 2kΩ
RL = 600Ω
±12
±11.5
±12.5
±12
±12
±11.5
±12.5
±12
V
V
ISSupply Current 7.5 10 7.8 11 mA
Minimum Supply Voltage (Note 5) ±5 ±5 V
Offset Adjustment Range RPOT ≥ 10k, Wiper to V+±4 ±10 ±4 ±10 mV
LT1122 4 L7LJ1W
LT1122
4
1122fb
For more information www.linear.com/LT1122
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V. (Note 2)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications
are at –55°C ≤ TA ≤ 125°C. VS = ±15V, VCM = 0V. (Note 2)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications
are at –40°C ≤ TA ≤ 85°C. VS = ±15V, VCM = 0V. (Note 6)
SYMBOL PARAMETER CONDITIONS
LT1122AC/BC
LT1122CC/DC
LT1122CS/DS
UNITSMIN TYP MAX MIN TYP MAX
VOS Input Offset Voltage l350 1400 400 2000 µV
Average Temperature Coefficient of
Input Offset Voltage
l5 18 6 25 µV/°C
IOS Input Offset Current l12 150 15 200 pA
IB Input Bias Current l80 600 90 800 pA
AVOL Large-Signal Voltage Gain VOUT = ±10V, RL ≥ 2kΩ l120 380 100 340 V/mV
CMRR Common-Mode Rejection Ratio VCM = ±10V l82 98 78 96 dB
PSRR Power Supply Rejection Ratio VS = ±10V to ±17V l84 101 80 99 dB
Input Voltage Range l±10 ±10.8 ±10 ±10.8 V
VOUT Output Voltage Swing RL = 2kΩ l±11.5 ±12.4 ±11.5 ±12.4 V
SR Slew Rate AV = –1 l50 70 40 65 V/µs
SYMBOL PARAMETER CONDITIONS
LT1122AM/BM LT1122CS/DS
UNITSMIN TYP MAX MIN TYP MAX
VOS Input Offset Voltage l650 2400 800 3400 µV
Average Temperature Coefficient of
Input Offset Voltage
l6 18 7 25 µV/°C
IOS Input Offset Current l0.5 6 0.6 9 nA
IBInput Bias Current l6 25 7 35 nA
AVOL Large-Signal Voltage Gain VOUT = ±10V, RL ≥ 2kΩ l70 230 60 200 V/mV
CMRR Common-Mode Rejection Ratio VCM = ±10V l80 97 76 94 dB
PSRR Power Supply Rejection Ratio VS = ±10V to ±17V l83 100 78 98 dB
Input Voltage Range l±10 ±10.5 ±10 ±10.5 V
VOUT Output Voltage Swing RL = 2kΩ l±11.3 ±12.1 ±11.3 ±12.1 V
SR Slew Rate AV = –1 l45 60 35 55 V/µs
SYMBOL PARAMETER CONDITIONS
LT1122AM/BM LT1122CS/DS
UNITSMIN TYP MAX MIN TYP MAX
VOS Input Offset Voltage l450 1900 500 2700 µV
Average Temperature Coefficient of
Input Offset Voltage
l6 20 7 28 µV/°C
IOS Input Offset Current l30 600 40 900 pA
IBInput Bias Current l230 2000 260 2700 pA
AVOL Large-Signal Voltage Gain VOUT = ±10V, RL ≥ 2kΩ l95 340 80 300 V/mV
CMRR Common-Mode Rejection Ratio VCM = ±10V l80 98 76 96 dB
PSRR Power Supply Rejection Ratio VS = ±10V to ±17V l83 100 78 98 dB
Input Voltage Range l±10 ±10.6 ±10 ±10.6 V
VOUT Output Voltage Swing RL = 2kΩ l±11.3 ±12.2 ±11.3 ±12.2 V
SR Slew Rate AV = –1 l45 60 35 60 V/µs
LT1122 g 5w 5w — m m M, M— u $9 r1» - 7 5H). SUMMWG NAEDUZ —W\A gDDE uwm Ll: wsm _ \s RES‘STGR CAN BE ADJUSTED m LL our ALL orrsns AT THE sgmwe muwur mnumrwuzu TESTER - smgpnwmumzm mow L7 LJUW 5
LT1122
5
1122fb
For more information www.linear.com/LT1122
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1122 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
Note 3: Settling time is 100% tested for A- and C-grades using the settling
time test circuit shown. This test is not included in quality assurance
sample testing.
Note 4: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 4mV
(A, B grades), to 5.7mV (C, D grades).
Note 5: Minimum supply voltage is tested by measuring offset voltage to
7mV maximum at ±5V supplies.
Note 6: The LT1122 is not tested and not quality-assurance-sampled
at –40°C and at 85°C. These specifications are guaranteed by design,
correlation and/or inference from –55°C, 0°C, 25°C, 70°C and/or 125°C
tests.
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15V
1µF TANT
0.1µF
1µF TANT
0.1µF
TYPICAL SUPPLY
BYPASSING FOR
EACH AMP/BUFFER
–10V
(REGULATED)
1
2
TTL
IN
4
5
74LS00
GROUND ALL
OTHER INPUTS
10V
(REGULATED)
6
3
SETTLING
TIME OUTPUT
(20 TIMES SUM
NODE OUTPUT)
1k
NO CONNECTION ON PINS
10, 11, 12, 14, AND 15
1N5712
15V
–15V
1.5k
LT1223
–
+3
2
4
7
6
81
7
2
5
4
1N5712
SUMMING
NODE
OUTPUT
–15V
15V
*THIS RESISTOR CAN BE ADJUSTED TO
NULL OUT ALL OFFSETS AT THE SETTLING
TIME OUTPUT. THE AUTOMATED TESTER
USES A SEPARATE AUTOZERO CIRCUIT.
–15V
(MEASURE INPUT
PULSE HERE)
VIN
5.1k
1%
4
–15V
3
27
6
LT1122
2k
1%
15V
2k
1%
DEVICE UNDER TEST
5pF
15V
7
1
5
2
851Ω
51Ω 51Ω
51Ω
+
–
HA5002
79Ω
5.1k*
1%
HA5002
4
LTC201A
LT1122•TA02
–15V
+
+
Settling Time Test Fixture
LT1122 6 L7HCU§QB
LT1122
6
1122fb
For more information www.linear.com/LT1122
TYPICAL PERFORMANCE CHARACTERISTICS
Settling Time
(Input from 0V to –10V) Large-Signal Response
Undistorted Output Swing
vs Frequency
Voltage Gain vs Frequency Gain, Phase vs Frequency
Common-Mode Rejection
vs Frequency
Settling Time
(Input from –10V to 0V)
Settling Time
(Input from 10V to 0V)
Settling Time
(Input from 0V to 10V)
100ns/DIV 1122 G01
1mV/DIV AT SUM NODE
100ns/DIV 1122 G02
1mV/DIV AT SUM NODE
100ns/DIV 1122 G03
1mV/DIV AT SUM NODE
100ns/DIV 1122 G04
1mV/DIV AT SUM NODE
200ns/DIVAV = 1 1122 G05
5V/DIV
FREQUENCY (Hz)
100k
0
PEAK-TO-PEAK OUTPUT SWING (V)
10
20
25
30
1M 10M 100M
V = ±15V
T = 25°C
15
5
S
A
1122 TPC01
FREQUENCY (Hz)
1
0
GAIN (dB)
20
40
60
80
100
120
10 100 1k 10k
–20
–40 100k 1M 10M 100M
V = ±15V
T = 25°C
S
A
1122 TPC02
FREQUENCY (Hz)
1M
10
GAIN (dB)
10
20
100M
10M
0
80
100
120
140
160
180
200
V = ±15V
T = 25°C
C = 15pF
S
A
L
PHASE SHIFT (DEGREES)
1122 TPC03
FREQUENCY (Hz)
100
0
COMMON-MODE REJECTION RATIO (dB)
20
40
60
80
100
120
1k 10k 1M 100M
V = ±15V
T = 25°C
S
A
100k 10M
1122 TPC04
LT1122 HAS CURRENT UFFSET N PACKAGE PACKAGE L7 LJUW 7
LT1122
7
1122fb
For more information www.linear.com/LT1122
TYPICAL PERFORMANCE CHARACTERISTICS
Warm-Up Drift Noise Spectrum 0.1Hz to 10Hz Noise
Total Harmonic Distortion + Noise
vs Frequency Inverting Gain
Total Harmonic Distortion + Noise
vs Frequency Noninverting Gain
Intermodulation Distortion
(CCIF Method) vs Frequency
LT1122 and LF156*
Distribution of Input Offset
Voltage
Input Bias and Offset Currents
Over Temperature
Bias and Offset Currents Over the
Common-Mode Range
INPUT OFFSET VOLTAGE (µV)
–900
0
NUMBER OF UNITS
200
400
600
800
–500 –100 100 500
V = ±15V
T = 25°C
(NOT WARMED UP)
S
A
3370 UNITS TESTED
IN ALL PACKAGES
1122 TPC05
900
CHIP TEMPERATURE (°C)
0
1
INPUT BIAS AND OFFSET CURRENTS (pA)
300
1k
3k
10k
25 50 75 100 125
100
30
10
3
BIAS
CURRENT
OFFSET
CURRENT
V = ±15V
V = 0V
S
CM
1122 TPC06
30k
100k
COMMON-MODE INPUT VOLTAGE (V)
15
0
INPUT BIAS AND OFFSET CURRENT (pA)
20
40
60
80
100
120
10 5 5 15
V = ±15V
T = 25°C
S
A
010
(NOT-WARMED UP)
BIAS
CURRENT
OFFSET
CURRENT
1122 TPC07
TIME AFTER POWER ON (MINUTES)
0
1
CHANGE IN OFFSET VOLTAGE (µV)
50
100
150
200
250
1 2 3
V = ±15V
T = 25°C
S
A
J PACKAGE
N PACKAGE
SO PACKAGE
IN STILL AIR (SO PACKAGE
SOLDERED ONTO BOARD)
1122 TPC08
FREQUENCY (Hz)
1
10
VOLTAGE NOISE DENSITY (nV/√Hz)
100
1000
3 10 10k
30 100 300 1k 3k
V = ±15V
T = 25°C
S
A
1122 TPC09
TIME (SECONDS)
0
NOISE VOLTAGE (1µV/DIV)
2 4 8 106
1122 TPC10
FREQUENCY (Hz)
20
0.0001
TOTAL HARMONIC DISTORTION + NOISE (%)
0.001
0.01
0.1
100 1k 20k
AV = –50
AV = –10
AV = –1
10k
T = 25°C
V = ±15V
Z = 5k//15pF
V = 7V RMS
A
S
L
O
1122 TPC11
FREQUENCY (Hz)
20
0.0001
TOTAL HARMONIC DISTORTION + NOISE (%)
0.001
0.01
0.1
100 1k 20k
AV = 50
AV = 10
AV =1
10k
T = 25°C
V = ±15V
Z = 5k//15pF
V = 7V RMS
A
S
L
O
1122 TPC12
FREQUENCY (Hz)
3k
0.0001
INTERMODULATION DISTORTION (IMD) (%)
0.001
0.01
0.1
10k 20k
LT1122
LF156
V = ±15V
T = 25°C
A = –10
V = 7V RMS
Z = 5k//15pF
S
A
V
O
L
*SEE LT1115 DATA SHEET FOR DEFINITION
OF CCIF TESTING
1122 TPC13
LT1122 L7LJCUEN2
LT1122
8
1122fb
For more information www.linear.com/LT1122
APPLICATIONS INFORMATION
Settling Time Measurements
Settling time test circuits shown on some competitive
devices’ data sheets require:
1. A “flat top” pulse generator. Unfortunately, flat top pulse
generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four-to-one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
3. A small inductor load to optimize settling.
The LT1122’s settling time is 100% tested in the test circuit
shown. No “flat top” pulse generator is required. The test
circuit can be readily constructed, using commercially
available ICs. Of course, standard high frequency board
construction techniques should be followed. All LT1122s
are measured with a constant feedback capacitor. No fine
tuning is required.
Speed Boost/Overcompensation Terminal
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting Pin 8 to the posi-
tive supply (Pin 7) increases slew rate and bandwidth by
about 25%, but at the expense of a reduction in phase
margin by approximately 18 degrees. Unity-gain capacitive
load handling decreases from typically 500pF to 100pF.
Conversely, connecting a 15k resistor from Pin 8 to ground
pulls 1mA out of Pin 8 (with V+ = 15V). This reduces slew
rate and bandwidth by 25%. Phase margin and capacitive
load handling improve; the latter typically increasing to
800pF.
High Speed Operation
As with most high speed amplifiers, care should be
taken with supply decoupling, lead dress and component
placement.
The power supply connections to the LT1122 must maintain
a low impedance to ground over a bandwidth of 20MHz.
This is especially important when driving a significant
resistive or capacitive load, since all current delivered to
the load comes from the power supplies. Multiple high
quality bypass capacitors are recommended for each power
supply line in any critical application. A 0.1µF ceramic and
a 1µF electrolytic capacitor, as shown, placed as close as
possible to the amplifier (with short lead lengths to power
supply common) will assure adequate high frequency
bypassing, in most applications.
V+
7
2
6
3
4
1µF 0.1µF
1µF 0.1µF
V–
LT1122
1122 TA03
+
–
+
+
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed-loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capaci-
tor (CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
RSCS
CIN
RF
CF
OUTPUT
+
–
1122 TA04
LT1122 L7 LJUW 9
LT1122
9
1122fb
For more information www.linear.com/LT1122
TYPICAL APPLICATIONS
Quartz Stabilized Oscillator With 9ppm Distortion
W
DISTORTION
TRIM
50k
430pF
560k
47k
4kHz
J
CUT
LT1010LT1122
+
–
LT1122
–15V
15V
2k
1/4 LTC201
GROUND CRYSTAL CASE
= VACTEC VTL5C10 OR
CLAIREX CLM410
= 1N4148
15V
1M 560k
100k
Q1
2N3904
15V
1122 TA05
–
+
4.7k
4.7k 5k
OUTPUT
AMPLITUDE
TRIM 10µF
470
LT1006
LT1004
2.5V
4.7k
–15V
OUTPUT
+
–
MOUNT IN CLOSE
PROXIMITY
+
LT1122 WWI—WW T l UUUU f7” ¢7flff /~\ H \_/ 74: 74 L74 7+” * * INCHES ‘IO L7LJCUEN2
LT1122
10
1122fb
For more information www.linear.com/LT1122
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LT1122 L7 LJUW 1 1
LT1122
11
1122fb
For more information www.linear.com/LT1122
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1 2 34
8 7 6 5
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
J8 Package
3-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
OBSOLETE PACKAGE
LT1122 i * ¢ 3 7 s 5 “JD [ET H H H H J 7 7 LDDDD * F ,7H H H H e Tm [DZUSinfiI i 7 7; Egpi LT 74‘9‘4: 1 2 L7LJflw
LT1122
12
1122fb
For more information www.linear.com/LT1122
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LT1122 L7HEJWEGR 1 3
LT1122
13
1122fb
For more information www.linear.com/LT1122
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REV DATE DESCRIPTION PAGE NUMBER
B 02/14 Updated data sheet to current standards. New Order Information Table, Package Descriptions 2, 10-12
REVISION HISTORY
(Revision history begins at Rev B)
LT] 122
LT1122
14
1122fb
For more information www.linear.com/LT1122
LINEAR TECHNOLOGY CORPORATION 1991
LT 0214 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT1122
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1022 High Speed Precision JFET Op Amp 23V/µs Min Slew Rate, 250µV VOS
LT1055/LT1056 Precision High Speed JFET Op Amps 16V/µs Slew Rate, 150µV VOS
LT1464 1MHz C-Load™ Stable JFET Op Amp Capacitive Loads Up to 10nF
LTC
®
6244 50MHz Low Noise CMOS Op Amp 1pA IB, 100µV Max VOS, 1.5µVP-P, 0.1Hz to 10Hz Noise
Wide-Band, Filtered, Full Wave Rectifier
IN
V
OUT
E DC
+
–
1µF
200k
1%
20k
1%
100k
1% 1k
50k
200k
1%
20k
1%
LT1122
OUTPUT DC = RMS VALUE OF INPUT
BANDWIDTH WITH 10VP-P INPUT = 2MHz
+
–
LT1122
1122 TA06