LTC3773 Datasheet by Analog Devices Inc.

L7L||‘|Ef\|2 TECHNOLOGY L7 LJUW
LTC3773
1
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FEATURES DESCRIPTION
Triple Output Synchronous
3-Phase DC/DC Controller with
Up/Down Tracking
The LTC®3773 is a high performance, 3-phase, triple output
synchronous step-down switching regulator controller
with output voltage power up/down tracking capability.
The controller allows for sequential, coincident or ratio-
metric tracking.
This 3-phase controller drives its output stages with 120°
phase separation at frequencies of up to 700kHz per phase
minimizing the RMS input current. Light load effi ciency can
be maximized by using selectable Burst Mode operation.
The 0.6V precision reference supports output voltages
from 0.6V to 5V.
Fault protection features include output overvoltage, input
undervoltage lockout plus current foldback under short-
circuit or overload conditions.
■ Servers, Telecom, Industrial Power Supplies
■ General Purpose Multiple Rail DC/DC
■ FPGA and DSP Requirements
■ Current Mode Controller with Onboard
MOSFET Drivers
■ Programmable Power Up/Down Tracking
■ Wide VIN Range: 3.3V to 36V (VCC = 5V)
■ ±1% 0.6V VFB Accuracy Over Temperature
■ Power Good Output Voltage Monitor
■ Phase-Lockable or Adjustable Frequency:
160kHz to 700kHz
■ OPTI-LOOP® Compensation Minimizes COUT
■ Current Foldback and Overvoltage Protection
■ Selectable Continuous, Discontinuous or
Burst Mode® Operation at Light Load
■ Programmable Phase Operation
■ Available in 5mm x 7mm QFN and 36-Lead
SSOP Packages
High Effi ciency, 3-Phase, Triple Synchronous DC/DC Step-Down Controller
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620,
6144194, 6177787, 6304066, 6498466, 6580258, 6611131.
+
0.003Ω
20k
10k
V
OUT2
1.8V/15A
V
IN
4.5V TO 22V
V
CC
4.5V TO 6V
C
IN
1.5μH
0.1μF
TG2
10k
PGOOD
POWER UP/SHUTDOWN SW2
BG2
TRACK1, 2, 3
TG1
SW1
BG1
SENSE1+
SENSE1–
V
FB1
I
TH1, 2, 3
SDB1, 2, 3
SW1, 2, 3
BOOST1, 2, 3
SENSE2+
LTC3773
PLLFLTR SGND
SENSE2–
V
FB2
V
DR
PGOOD V
CC
TG3
SW3
BG3
PGND
SENSE3+
SENSE3–
V
FB3
C
OUT2
V
IN
0.003Ω
20k
20k
V
OUT3
1.2V/15A
C
OUT3
10μF
1.2μH
V
IN
0.003Ω
31.6k 10k
V
OUT1
2.5V/15A
C
OUT1
2.2μH
0.01μF
3773 F01
TYPICAL APPLICATION
APPLICATIONS
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LTC3773
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PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
Topside Driver Voltage (BOOSTn) ..............42V to –0.3V
Switch Voltage (SWn) ...................................36V to –1V
Boosted Driver Voltage (BOOSTn – SWn) .... 7V to –0.3V
Supply Voltages (VCC, VDR) ..........................7V to –0.3V
PGOOD, PHASEMD, PLLFLTR, PLLIN/FC, SDBn,
TRACKn, VFBn ...............................(VCC + 0.3V) to –0.3V
SENSE+n, SENSE–n ........................ (1.1 • VCC) to –0.3V
ITHn Voltage ...............................................2.7V to –0.3V
(Note 1)
Extended Commercial Operating
Temperature Range (Note 2) ................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range ...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
G Package ......................................................... 300°C
Peak Body Temperature UHF Package................... 240°C
TJMAX = 125°C, θJA = 95°C/W
TJMAX = 125°C, θJA = 34°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PHASEMD
PGOOD
BOOST1
TG1
SW1
SW2
TG2
BOOST2
BOOST3
TG3
SW3
BG1
BG2
VDR
PGND
BG3
PLLIN/FC
PLLFLTR
SENSE1+
SENSE1–
SDB
TRACK1
VFB1
ITH1
SGND
ITH2
ITH3
VFB2
VFB3
TRACK2
TRACK3
SENSE2–
SENSE2+
SENSE3–
SENSE3+
VCC
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS PGND (PIN 39),
MUST BE SOLDERED TO PCB
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1TRACK1
VFB1
ITH1
SGND
ITH2
ITH3
VFB2
VFB3
TRACK2
TRACK3
SENSE2–
SENSE2+
BOOST1
TG1
SW1
SW2
TG2
BOOST2
BOOST3
TG3
SW3
BG1
BG2
VDR
SDB3
SDB2
SDB1
SENSE1–
SENSE1+
PHASEMD
PGOOD
SENSE3–
SENSE3+
VCC
PLLFLTR
PLLIN/FC
CLKOUT
BG3
23
22
21
20
9
10
11
12
ORDERING INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3773EG#PBF LTC3773EG#TRPBF 36-Lead Plastic SSOP –40°C to 85°C
LTC3773EUHF#PBF LTC3773EUHF#TRPBF 3773E 38-Lead (5mm x 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC3773 L7 LJUW
LTC3773
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
VFB Feedback Voltage VITH = 1.2V, 0°C ≤ T ≤ 85°C (Note 4)
●
0.594
0.591
0.600
0.600
0.606
0.609
V
V
IVFB Feedback Pin Input Current 0 ≤ VFB ≤ 1V –15 –100 nA
VSENSEMAX Maximum Current Sense Threshold VFB = 0.55V, VTRACK = 1V, VSENSE– = 2.5V
●
65
60
75
75
85
90
mV
mV
VFBLOADREG Feedback Voltage Load Regulation Measured in Servo Loop (Note 4)
ΔITH Voltage = 1.2V to 0.7V
ΔITH Voltage = 1.2V to 2V
●
●
0.15
–0.2
0.5
–0.5
%
%
VFBLNREG Feedback Voltage Line Regulation VCC = 4.5V to 6V 0.01 %/V
gmTransconductance Amplifi er gmVITH = 1.2V, Sink/Source 25μA (Note 4) ●2.3 2.7 3.2 mmho
fuTransconductance Amplifi er GBW VITH = 1.2V (Note 5) 3 MHz
AERR Transconductance Amplifi er DC Gain VITH = 0.8V to 1.6V ●50 56 dB
VUVR VCC Undervoltage Reset
Undervoltage Hysteresis
VCC Ramping Positive 3.7 4.1
0.16
4.4 V
V
VCC VCC Supply Voltage ●4.5 5 6 V
IVCC VCC Supply Current
Normal Mode
Shutdown
VCC = 5V
VSDB = 0V
2.8
20
4
30
mA
μA
IVDR VDR Supply Current
Normal Mode
Shutdown
VDR = 5V (Note 6)
VSDB = 0V
5
1
mA
μA
IBOOST VBOOST Supply Current
Normal Mode
Shutdown
VBOOST = 5V, VSW = 0V (Note 6)
VSDB = 0V
1
1
mA
μA
ISDB SDB Source Current
SDB1, SDB2, SDB3 Source Content
–1.5
–0.5
μA
μA
VSDB SDB Power Up Threshold
SDB1 Pin CH1 ON Threshold
SDB2 Pin CH2 ON Threshold
SDB3 Pin CH3 ON Threshold
Ramping Positive ●
●
●
●
0.4
1.14
1.71
2.3
1.2
1.8
2.4
1.26
1.89
2.5
V
V
V
V
Channel On Threshold Hysteresis –10 %
ISENSE SENSE Pins Source Current VSENSE+, VSENSE– = 1.2V, Current at Each Pin –13 –20 μA
DFMAX Maximum Duty Factor PLLFLTR Floats, In Dropout 97 98.5 %
TG RUP TG Driver Pull-Up On-Resistance TG High, IOUT = 100mA (Note 7) 2.2 Ω
TG RDOWN TG Driver Pull-Down On-Resistance TG Low, IOUT = 100mA (Note 7) 1.8 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High, IOUT = 100mA (Note 7) 2.4 Ω
BG RDOWN BG Driver Pull-Down On-Resistance BG Low, IOUT = 100mA (Note 7) 0.9 Ω
TG/BG t1D Top Gate OFF to Bottom Gate ON Delay
Synchronous Switch-On Delay Time
All Controllers 50 ns
BG/TG t2D Bottom Gate OFF to Top Gate ON Delay
Top Switch-On Delay Time
All Controllers 50 ns
tON(MIN) Minimum On-Time Tested with a Square Wave (Note 8) 130 ns
Tracking
ITRACK TRACK Pin Pull-Up Current VSDB = 5V, VTRACK = 0V –1 μA
VFBTRACK VFB Voltage During Tracking VTRACK = 0.2V, VITH = 1.2V (Note 4)
VTRACK = 0.4V, VITH = 1.2V (Note 4)
180
380
200
400
220
420
mV
mV
ELECTRICAL CHARACTERISTICS
(Note 3) The ● denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = VDR = VBOOST = VSDB = 5V, unless otherwise noted.
LTC3773 L7LJCUEN2
LTC3773
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3773 is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. TJ is calculated from the ambient
temperature TA and power dissipation PD according to the following
formula.
LTC3773EG: TJ = TA + (PD x 95°C/W)
LTC3773EUHF: TJ = TA + (PD x 34°C/W)
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specifi ed.
Note 4: The IC is tested in a feedback loop that adjusts VFB to achieve a
specifi ed error amplifi er output voltage (VITH).
Note 5: Guaranteed by design, not subject to test.
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 7: RDS(ON) limit is guaranteed by design and/or correlation to static
test.
Note 8: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current of ≥40% of IMAX (see minimum on-time
considerations in the Applications Information section).
(Note 3) The ● denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = VDR = VBOOST = VSDB = 5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Good Output Indication
VPGL PGOOD Voltage Output Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Output Leakage VPGOOD = 5V 1 μA
VPGTHNEG
VPGTHPOS
PGOOD Trip Thresholds
VFB Ramping Negative
VFB Ramping Positive
VFB with Respect to 0.6V Reference
PGOOD Goes Low After VPGDLY Delay –7
7
–10
10
–13
13
%
%
VPGDLY PGOOD Delay 100 150 μs
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VPLLFLTR Open 360 400 440 kHz
fLOW Low Frequency VPLLFLTR = 0V 190 220 250 kHz
fHIGH High Frequency VPLLFLTR = 5V 510 560 630 kHz
fPLLLOW PLLIN Minimum Input Frequency 160 200 kHz
fPLLHIGH PLLIN Maximum Input Frequency 540 700 kHz
VLO
VFLOAT
VHI
PLLIN/FC, PHASEMD, PLLFLTR
Logic Input
Low Level Input Voltage
Floating Voltage
High Level Input Voltage
1.0
1.6
3.0
V
V
V
VPLLIN PLLIN Synchronization Input Threshold 1 V
IPLLFLTR Phase Detector Output Current
Sinking Capability
Sourcing Capability
VPLLFLTR = 1.5V
fPLLIN < fOSC
fPLLIN > fOSC
25
–25 μA
μA
PRELPHS Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
PHASEMD Floats or VPHASEMD = 0V 120
240
Deg
Deg
Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
VPHASEMD = 5V 90
270
Deg
Deg
CLKOUT Controller 1 TG to CLKOUT Phase PHASEMD Floats
VPHASEMD = 0V
VPHASEMD = 5V
0
60
180
Deg
Deg
Deg
L7 LJUW 725 LTC3773 4n RSENSE =
LTC3773
5
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LOAD CURRENT (A)
0
ΔVOUT (mV)
NORMALIZED ΔVOUT (%)
–10
–5
5
0
3773 G04
–15
–20
–25
–0.4
–0.2
0.2
0.0
–0.6
–0.8
–1.0
510 15 20
VIN = 12V, VCC = 5V, VOUT = 2.5V
CONTINUOUS MODE
DISCONTINUOUS MODE
Burst Mode OPERATION
TYPICAL PERFORMANCE CHARACTERISTICS
Effi ciency vs Load Current,
Shutdown CH2 and CH3
CHANNEL 1 LOAD CURRENT (A)
VIN = 12V, VCC = 5V, VOUT1 = 2.5V
fSW = 220kHz
20
CHANNEL 1 EFFICIENCY (%)
POWER LOSS (mW)
40
30
10
60
80
70
50
90
100
0.001 0.01 0.1 1 10 100
3773 G01
0
1
10
100
1000
10000
0.1
EFFICIENCY
POWER LOSS
CONTINUOUS
MODE
DISCONTINUOUS
MODE
Burst Mode
OPERATION
Effi ciency vs VIN
Shutdown CH2 and CH3 Load Regulation
VIN (V)
0
CHANNEL 1 EFFICIENCY (%)
POWER LOSS (W)
90
95
100
20
3773 G03
85
80
75
2.4
3.2
4.0
1.6
0.8
0.0
510 15 25
PLLFLTR = 5V
fSW = 560kHz
PLLFLTR FLOATS
fSW = 400kHz
PLLFLTR = 0V
fSW = 220kHz
EFFICIENCY
POWER LOSS
VCC = 5V, VOUT1 = 2.5V, IOUT1 = 5A
SHUTDOWN CH2 AND CH3
CHANNEL 1 LOAD CURRENT (A)
VIN = 12V, VCC = 5V, VOUT1 = 2.5V
VOUT2 = 1.8V (NO LOAD), VOUT3 = 1.2V (NO LOAD)
fSW = 220kHz
20
CHANNEL 1 EFFICIENCY (%)
POWER LOSS (mW)
40
30
10
60
80
70
50
90
100
0.001 0.01 0.1 1 10 100
3773 G02
0
1
10
100
1000
10000
0.1
EFFICIENCY
POWER LOSS
DISCONTINUOUS
MODE
Burst Mode
OPERATION
CONTINUOUS
MODE
VIN (V)
0
ΔVOUT (mV)
NOMALIZED ΔVOUT (mV/V)
0.5
1.5
1.0
2.0
2.5
20
3773 G05
–0.5
–1.0
0
–1.5
–2.0
–2.5
0.2
0.6
0.4
0.8
1.0
–0.2
–0.4
0
–0.6
–0.8
–1.0
510 15 25
VCC = 5V, VOUT = 2.5V, IOUT = 5A
Current Limit vs VIN
VIN (V)
0
MAXIMUM LOAD CURRENT (A)
15
20
25
20
3773 G06
10
5
0510 15 25
VCC = 5V, VOUT = 2.5V, fSW = 220kHz
RSENSE = 3mΩ
RSENSE = 5mΩ
Effi ciency vs Load Current,
Power-Up CH2 and CH3
Line Regulation
LTC3773 L7Hߤߤ
LTC3773
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SWITCHING FREQUENCY (kHz)
150
IVDR (mA)
IVCC (mA)
80
100
120
650 750550
3773 G07
40
60
20
0
2.4
2.5
2.6
2.2
2.3
2.1
2.0
250 350 450
VIN = 10V, VCC = VDR = 5V,
FORCED CONTINUOUS MODE
VOUT1 = 2.5V WITH 5A LOAD
VOUT2 = 1.8V WITH 5A LOAD
VOUT3 = 1.2V WITH 5A LOAD
IVDR
IVCC
3773 G09
1.8V VOUT
50mV/DIV
AC COUPLED
ILOAD
10A/DIV
IL
5A/DIV
50μs/DIV
VIN = 12V, fSW = 220kHz
3773 G11
1.8V VOUT
50mV/DIV
AC COUPLED
ILOAD
5A/DIV
50μs/DIV
IL
5A/DIV
VSW
10V/DIV
VIN = 12V, fSW = 220kHz
TYPICAL PERFORMANCE CHARACTERISTICS
IVDR and IVCC vs Switching Frequency
Forced Continuous Mode
0A to 10A Load Step
Discontinuous Mode 0A to 5A
Load Step at 5kHz Interval
IVCC and IVDR vs Load Current
Burst Mode Operation 0A to 5A
Load Step at 5kHz Interval
CHANNEL 1 LOAD CURRENT (A)
0.001
1
IVCC + IVDR (mA)
100
0.01 0.1 1 10 100
3773 G08
10
FORCED CONTINUOUS
VIN = 12V, VCC = VDR = 5V, VOUT1 = 2.5V
VOUT2 = 1.8V (NO LOAD), VOUT3 = 1.2V (NO LOAD)
DISCONTINUOUS
MODE
Burst Mode
OPERATION
PLLFLTR = 0V
PLLFLTR = 5V
PLLFLTR = FLOATS
3773 G10
1.8V VOUT
50mV/DIV
AC COUPLED
ILOAD
5A/DIV
50μs/DIV
IL
5A/DIV
VSW
10V/DIV
VIN = 12V, fSW = 220kHz
LTC3773 // L7 LJUW
LTC3773
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TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Limit
Threshold vs Duty Factor
TEMPERATURE (°C)
–50
VFB (mV)
ΔVFB (%)
603.0
604.5
606.0
100 12575
3773 G12
597.0
598.5
601.5
600.0
595.5
594.0
0.50
0.75
1.00
–0.50
–0.25
0.25
0
–0.75
–1.00
–25 025 50
Error Amplifi er gm
vs Temperature
Maximum Current Limit
Threshold vs Temperature
Maximum Current Limit
Threshold vs VITH
TEMPERATURE (°C)
–50
ERROR AMPLIFIER gm (mmho)
3.1
3.2
100 12575
3773 G13
2.7
2.8
3.0
2.9
2.6
2.5
2.4
2.3 –25 025 50
TEMPERATURE (°C)
–50
VSENSE (mV)
ΔVSENSE (%)
84
100 12575
3773 G14
75
81
78
72
69
66
12
0
8
4
–4
–8
–12
–25 025 50
VSENSE – = 5V
VSENSE – = 2.5V
VSENSE – = 0.6V
VITH (V)
0
VSENSE (mV)
80
2.4 2.72.11.8
3773 G15
40
60
20
0
–20
–40 0.3 0.6 0.9 1.2 1.5
VFB = 0.58V
VSENSE COMMON MODE VOLTAGE (V)
0
VSENSE (mV)
90
5 5.54.543.53
3773 G16
75
78
87
84
81
69
72
66
63
60 0.5 1 1.5 2 2.5
VCC = 5V
VFB = 0.58V
DUTY FACTOR (%)
0
VSENSE (mV)
80
10090807060
3773 G17
50
70
60
30
40
20
10
010 20 30 40 50
VFB vs Temperature
Maximum Current Limit
Threshold vs SENSE Common
Mode Voltage
LTC3773 Mm = W vac = 5v ‘SENSE = ‘sENsE‘ = ISENSE’ - - Mam L \ SEDkHz L7 LINEAR v toerch
LTC3773
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VSENSE COMMON MODE VOLTAGE (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
ISENSE (μA)
40
3773 G19
20
30
0
10
–10
–20
–30
VCC = 5V
ISENSE = ISENSE+ = ISENSE–
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
SWITCHING FREQUENCY (kHz)
650
3773 G20
550
600
350
450
400
500
300
250
200
150
VPLLFLTR = 5V
PLLFLTR FLOATING
VPLLFLTR = 0V
VPLLFLTR (V)
0 0.5 1 1.5 2 2.5 3
SYNCHRONIZATION SWITCHING FREQUENCY (kHz)
800
3773 G21
700
400
500
600
300
200
100
VCC = 5V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
TG MINIMUM PULSE WIDTH (ns)
180
3773 G22
140
160
120
100
VSENSE = 100mV STEP
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
MAXIMUM DUTY FACTOR (%)
100
3773 G23
92
96
88
84
80
DROPOUT
TG, BG OPEN
VPLLFLTR = 0V
PLLFLTR FLOATING
VPLLFLTR = 5V
VPLLFLTR = 0V, fSW = 220kHz
VPLLFLTR FLOATING, fSW = 400kHz
VPLLFLTR = 5V, fSW = 560kHz
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE Pin Input Current vs
SENSE Common Mode Voltage
Switching Frequency
vs Temperature
Synchronization Switching
Frequency vs VPLLFLTR
TG Minimum Pulse Width
vs Temperature
Maximum Duty Factor
vs Temperature
Maximum Current Limit
Threshold vs VFB
VFB (mV)
0
VSENSE (mV)
80
600500400
3773 G18
50
70
60
30
40
20
10
0100 200 300
VTRACK = 1V
LTC3773 ‘mcx 52 / 5032 SH “‘\‘ L7 LJUW
LTC3773
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TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VCC UNDERVOLTAGE RESET (V)
4.4
3773 G24
4.2
4.1
4.3
4.0
3.9
3.8
3.7
POWER UP
SHUTDOWN
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
PULLUP CURRENT (μA)
1.2
3773 G25
0.9
0.6
0.3
0
ISDB2
ITRACK
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
PGOOD DELAY (μs)
180
3773 G26
170
160
150
140
130
110
120
100
PGOOD ↑
PGOOD ↓
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
THRESHOLD VOLTAGE (V)
3.3
3773 G27
2.9
2.5
2.1
1.7
1.3
0.9
0.5
HIGH THRESHOLD
FLOATING THRESHOLD
LOW THRESHOLD
VCC = 5V
VCC Undervoltage Reset Voltage
vs Temperature
TRACK and SDB Pull-Up Current
vs Temperature
PGOOD Delay vs Temperature
PLLIN/FC, PHASEMD, PLLFLTR,
Threshold Voltage vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
THRESHOLD VOLTAGE (V)
2
3773 G28
1
1.5
0.5
0
CHANNEL 2 ENABLE
CHANNEL 2 DISABLE
SDB2 SHUTDOWN
VCC = 5V
SDB2 Threshold Voltage
vs Temperature
LTC3773 L7LJCUEN2
LTC3773
10
3773fb
SENSE1+ (Pin 1/Pin 34): The (+) Input to the Channel 1
Differential Current Comparator. The ITH1 pin voltage and
controlled offsets between the SENSE1– and SENSE1+
pins in conjunction with RSENSE set the channel 1 current
trip threshold.
SENSE1– (Pin 2/Pin 35): The (–) Input to the Channel 1
Differential Current Comparator.
SDB/SDB1, SDB2, SDB3 (Pin 3/Pins 36, 37, 38): Shut-
down, Active Low. For G package, SDB1, SDB2 and SDB3
are shorted at the SDB pin. The power up thresholds for
channel 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V respec-
tively. By pulling the SDB1, SDB2 and SDB3 pins below
0.4V, the IC is put into low current shutdown mode (IVCCQ
<30μA). There is a 0.5μA pull-up current at each SDB pin.
An external capacitor can be added at this pin to provide
power up delay.
TRACK1 (Pin 4/Pin 1): Channel 1 Tracking Input. TRACK1
is used for tracking multiple LTC3773s. See the Startup
Tracking application. To disable this feature, fl oat this pin
or tie it to VCC. TRACK1 provides a 1μA pull-up current.
An external capacitor can be added at this pin to provide
soft-start. During startup or output short-circuit condition,
if the potential at TRACK1 is less than 0.54V, current limit
foldback is disabled. When channel 1 is powered down,
this pin will be pulled low.
VFB1 (Pin 5/Pin 2): Channel 1 Error Amplifi er Feedback
Input. This pin connects the error amplifi er input to an
external resistive divider from VOUT1.
ITH1 (Pin 6/Pin 3): Channel 1 Error Amplifi er Output and
Switching Regulator Compensation Point. The current
comparator’s threshold increases with this control volt-
age.
SGND (Pin 7/Pin 4): Signal Ground. This pin must be
routed separately under the IC to the PGND pin and then
to the main ground plane.
ITH2 (Pin 8/Pin 5): Channel 2 Error Amplifi er Output and
Switching Regulator Compensation Point. See ITH1.
ITH3 (Pin 9/Pin 6): Channel 3 Error Amplifi er Output and
Switching Regulator Compensation Point. See ITH1.
VFB2 (Pin 10/Pin 7): Channel 2 Error Amplifi er Feedback
Input. See VFB1.
VFB3 (Pin 11/Pin 8): Channel 3 Error Amplifi er Feedback
Input. See VFB1.
TRACK2 (Pin 12/Pin 9): Channel 2 Tracking Input. Tie the
TRACK2 pin to a resistive divider connected to the output
of channel 1 for either coincident or ratiometric output
tracking. See the Soft-Start/Tracking application. TRACK2
comes with a 1μA pull-up current. An external capacitor
can be added at this pin to provide soft-start. During
startup or output short-circuit condition, if the potential
at TRACK2 is less than 0.54V, current limit foldback is
disabled. When channel 2 is powered down, this pin will
be pulled low.
TRACK3 (Pin 13/Pin 10): Channel 3 Tracking Input. See
TRACK2.
SENSE2– (Pin 14/Pin 11): The (–) Input to the Channel 2
Differential Current Comparator. See SENSE1–.
SENSE2+ (Pin 15/Pin 12): The (+) Input to the Channel 2
Differential Current Comparator. See SENSE1+.
SENSE3– (Pin 16/Pin 13): The (–) Input to the Channel 3
Differential Current Comparator. See SENSE1–.
SENSE3+ (Pin 17/Pin 14): The (+) Input to the Channel 3
Differential Current Comparator. See SENSE1+.
VCC (Pin 18/Pin 15): Main Input Supply. All internal circuits
except the output drivers are powered from this pin. VCC
should be connected to a low noise 5V power supply and
should be bypassed to SGND with at least a 1μF capacitor
in close proximity to the LTC3773.
PLLFLTR (Pin 19/Pin 16): Phase-Locked Loop Lowpass
Filter. The phase-locked loop’s lowpass fi lter is tied to this
pin. Alternatively, when external frequency synchronizing
is not used, this pin can be forced low, left fl oating or tied
high to vary the frequency of the internal oscillator.
PIN FUNCTIONS
(G/UHF)
LTC3773 L7 LJUW
LTC3773
11
3773fb
PLLIN/FC (Pin 20/Pin 17): Synchronization Input to the
Phase Detector and Forced Continuous Control Input.
When fl oating, it sits around 1.6V, and the controller enters
discontinuous mode operation at light load. Shorting this
pin low or high for more than 20μs enables Burst Mode
operation or forced continuous current mode operation,
respectively. During frequency synchronization, the phase
locked loop will force the controller to operate in continu-
ous mode and the rising top gate signal of controller 1 to
be synchronized with the rising edge of the PLLIN signal.
When synchronization is not required, it is advisable to
bypass the PLLIN/FC pin with a 1000pF capacitor to avoid
noise coupling.
CLKOUT (Pin 18 UHF Only): CLK Output. Output clock
signal available to synchronize other controller ICs for
additional MOSFET controller stages/phases.
BG3 (Pin 21/Pin 19): Channel 3 Bottom Gate Drive. See
BG1.
PGND (Pin 22/Pin 39): Driver’s Power Ground. This pin
connects directly to the sources of the bottom N-channel
external MOSFETs and the (–) terminals of CIN. The backside
exposed pad (QFN) must be soldered to PCB ground.
VDR (Pin 23/Pin 20): Driver Supply. Provides supply to the
drivers for the bottom gates. Also used for charging the
bootstrap capacitors. This pin needs to be very carefully
and closely decoupled to the IC’s PGND pin. If the VDR
potential is lower than VCC potential by 1V, the drivers
will be disabled.
BG2 (Pin 24/Pin 21): Channel 2 Bottom Gate Drive. See
BG1.
BG1 (Pin 25/Pin 22): Channel 1 Bottom Gate Drive. Drives
the gate of the bottom N-channel MOSFET between ground
and VDR.
SW3 (Pin 26/Pin 23): Channel 3 Switching Node. See
SW1.
TG3 (Pin 27/Pin 24): Channel 3 Top Gate Drive. See
TG1.
BOOST3 (Pin 28/Pin 25): Channel 3 Top Gate Driver Sup-
ply. See BOOST1.
BOOST2 (Pin 29/Pin 26): Channel 2 Top Gate Driver Sup-
ply. See BOOST1.
TG2 (Pin 30/Pin 27): Channel 2 Top Gate Drive. See TG1.
SW2 (Pin 31/Pin 28): Channel 2 Switching Node.
See SW1.
SW1 (Pin 32/Pin 29): Channel 1 Switching Node. The (–)
terminal of the bootstrap capacitor connects here. This
pin swings from a Schottky diode (external) voltage drop
below ground to VIN (where VIN is the external MOSFET
supply rail).
TG1 (Pin 33/Pin 30): Channel 1 Top Gate Drive. The TG1
pin drives the top N-channel MOSFET with a voltage
swing equal to VDR superimposed on the switch node
voltage SW.
BOOST1 (Pin 34/Pin 31): Channel 1 Top Gate Driver Supply.
The (+) terminal of the bootstrap capacitor connects here.
This pin swings from approximately VDR up to VIN + VDR
(where VIN is the external MOSFET supply rail).
PGOOD (Pin 35/Pin 32): Open Drain Power Good Output.
This open-drain output is pulled low during shutdown or
when any of the three output voltages has been outside
the PGOOD tolerance window for more than 100μs.
PHASEMD (Pin 36/Pin 33): Phase Select Input. This pin
controls the phase relationship between controller 1,
controller 2, controller 3 and CLKOUT. When PHASEMD
is fl oating, its value is around 1.6V, the three channels
switch 120° out of phase, and CLKOUT synchronizes to
the rising edge of TG1. When PHASEMD is grounded,
TG1 leads CLKOUT by 60°. When PHASEMD is shorted
to VCC, TG1 leads TG2, TG3, and CLKOUT by 90°, 270°
and 180°, respectively.
PIN FUNCTIONS
(G/UHF)
LTC3773 777777 L7LJCUEN2
LTC3773
12
3773fb
Figure 1. Functional Diagram
BOOST
TG
SW
VDR
BG
PGND
SENSE+
SENSE–
+
–
+
–
+
–
+
–
+–
+–
+–
+
–
+
–
PHASE DET
OSCILLATOR
+–
0.54V
0.6225V
0.66V
CLK3
CLK2
CH3 PBAD
CH2 PBAD
CH1 PBAD
100s
DELAY
PGOOD
CLKOUT PHASEMD
VFB
ITH
1V
0.5V
3V
+
–
+
–
SWITCH
LOGIC
FORCE CONT
FORCE BOT
DROP
OUT
DET
S
R
Q
Q
TOP ON
RS
LATCH
SHDN
SLEEP
+–
+–
3mV
I1I2
TOP
BOT
BOT
+
VDR
RLP
VIN
FIN
CIN
DB
CB
CLP
PLLFLTR
PLLIN/FC
RSENSE
L
VCC
VCC
CC
VCC
RC
VDR
VCC
OV
EA
0.6V
TRACK 5.3 x VFB
0.645V
1.8V
DUPLICATE FOR CH2 AND CH3
SLOPE
COMP
SLOPE
COMP
+
–
+
+
54k 54k
2.4V
VOUT
+
+–
2.4V 1.8V 1.2V
SDB3 SDB2 SDB1
R2
R1
SHDN
DRV SDB3SDB2
CH3
SHDN
CH2
SHDN
CH1
SHDN MASTER
SHDN UV
RESET
INTERNAL
SUPPLY
3.94V
CVCC
COUT
VREF
0.6V
SGND
VCC
VCC
+
3773 F01
VCC
36k
36k
CLK1
ENABLE
BURST
FUNCTIONAL DIAGRAM
LTC3773 L7 LJUW
LTC3773
13
3773fb
Main Control Loop
The LTC3773 uses a constant frequency, current mode
step down architecture. During normal operation, each
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of the error
amplifi er EA. The error amplifi er input pin, VFB, receives the
output voltage feedback signal from an external resistor
divider. This feedback signal is compared to the internal
0.6V reference voltage by the EA. When the load current
increases it causes a slight decrease in VFB relative to the
0.6V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. While the top N-channel MOSFET is off,
the bottom N-channel MOSFET is turned on until either the
next cycle begins or the inductor current starts to reverse,
as indicated by the current reversal comparator, I2.
The top MOSFET drivers are biased from fl oating boot-
strap capacitor CB, which is normally recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to VOUT, however, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically triggers a brief refresh pulse
to recharge CB.
Shutdown, Soft-Start and Tracking Startup
The main control loop is enabled by allowing the SDBn pin
to go high. In the G package, SDB1, SDB2 and SDB3 are
shorted together at the SDB pin. The power-up thresholds
for channels 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V
respectively. By forcing the SDB1, SDB2 and SDB3 pins
below 0.4V, the IC enters low current shutdown mode, and
the chip draws less than 30μA. Releasing SDBn allows an
internal 0.5μA current source to pull up the SDBn pin. If
a resistive divider connected to VIN drives the SDB pin,
the controller will automatically start up when VIN is fully
powered up.
The start-up of VOUT is controlled by the LTC3773’s TRACK
pin. An external capacitor at the TRACK pin provides the
soft-start function. During soft-start, the error amplifi er
EA compares the feedback signal, VFB, to the TRACK pin’s
potential (instead of the 0.6V reference), which rises linearly
from 0V to 0.6V. This allows the output voltage to rise
smoothly from 0V to its fi nal value while maintaining control
of the inductor current. When the potential at the TRACK
pin approaches the 0.6V reference voltage, the control
loop servos VFB to the internal reference. The TRACK pin
can also be used for power up/down tracking. A resistor
divider on VOUT1 connected to the TRACK2/TRACK3 pin
allows the startup of VOUT2/VOUT3 to track that of VOUT1
(refer to the Soft-Start/Tracking section for more detail).
Low Current Operation
The PLLIN/FC pin is a multifunction pin: 1) an external
clock input for PLL synchronization, and 2) a logic input
to select between three modes of operation.
A) Continuous Current Operation: When the PLLIN/FC
pin voltage is above 3V or driven by an external oscil-
lator, the controller performs as a continuous, PWM
current mode synchronous switching regulator. The
top and bottom MOSFETs are alternately turned on to
maintain the output voltage independent of direction
of inductor current. This is the least effi cient light load
operating mode, but has lowest output ripple. The
output can source or sink current in this mode. When
sinking current while in forced continuous operation,
the controller can cause current to fl ow back into the
input supply fi lter capacitor. Be sure to use an input
capacitor with enough capacitance to prevent the input
voltage from boosting too high. See CIN and COUT Se-
lection in the Applications Information section. Certain
applications must not allow continuous operation at
startup with prebiased output or power down; this can
be easily avoided by shorting the PGOOD output to the
PLLIN/FC pin. The controller will be forced to operate
in Burst Mode until all three outputs are within 10%
of their nominal values.
B) Burst Mode Operation: When the PLLIN/FC pin volt-
age is below 1V and the regulated output voltage is
within 10% of its nominal value, the controller behaves
(Refer to the Functional Diagram)
OPERATION
LTC3773 L7LJCUEN2
LTC3773
14
3773fb
as a Burst Mode switching regulator. Burst Mode op-
eration clamps the minimum peak inductor current to
approximately 20% of the current limit programmed
by RSENSE. As the load current goes down, the EA will
reduce the voltage on the ITH pin. When the ITH voltage
drops below 0.5V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.
In Burst Mode operation, the load current is supplied
by the output capacitor. As the output voltage falls,
the ITH voltage rises. When the ITH voltage reaches
0.55V, the SLEEP signal goes low and the controller
resumes normal operation by turning on the external
top MOSFET at the next cycle of the internal oscillator.
During Burst Mode operation, the inductor current is
not allowed to reverse.
C) Discontinuous Mode Operation: When the PLLIN/FC
pin is fl oating, Burst Mode operation is disabled but
the inductor current is not allowed to reverse. The 20%
minimum inductor current clamp present in Burst Mode
operation is removed, providing constant frequency
discontinuous operation over the widest possible output
current range. This constant frequency operation is not
quite as effi cient as Burst Mode operation, but provides
a lower noise, constant frequency spectrum.
Frequency Synchronization
The selection of switching frequency is a trade off between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN/FC
pin. The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator, which
operates over a 160kHz to 700kHz range corresponding
to a voltage input from 0V to 2.5V. When locked, the PLL
aligns the turn on of the controller 1 top MOSFET to the
rising edge of the synchronizing signal.
When PLLIN/FC is not being driven by an external clock
source, the PLLFLTR can be fl oated, tied to VCC or SGND
to select 400kHz, 560kHz or 220kHz switching frequency,
respectively.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on under
shutdown state or if any regulator output voltage has
been away from its nominal value by greater than 10%
for more than 100μs. To shut off this MOSFET, all three
regulator output voltages must be within the ±10% window
for more than 100μs.
Short-Circuit Protection and Current Foldback
Upon start-up, the soft-start action at the TRACK pin limits
the inrush current from the input power source; yet the
controller provides the maximum rated output current to
charge up the output capacitor as quickly as possible. If
TRACK ramps above 0.54V but the output voltage is less
than 70% of its nominal value, foldback current limiting is
activated on the assumption that the output is in a severe
overcurrent and/or short-circuit condition.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 3.75% above
the reference voltage of 0.6V, the top gate is turned off
and the bottom gate is turned on until the overvoltage is
cleared.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
VCC supply levels, an undervoltage lockout is incorporated
in the LTC3773. When VCC drops below 3.9V, the MOSFET
drivers and all internal circuitry are turned off except for the
undervoltage block and SDB input circuitry. If VDR is lower
than VCC by more than 1V, the drivers are disabled.
(Refer to the Functional Diagram)
OPERATION
LTC3773 VOUT VOUT L7 LJUW
LTC3773
15
3773fb
The basic application circuit is shown on the fi rst page
of this data sheet. External component selection is
driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltage ripple requirements. Once the inductors and oper-
ating frequency have been chosen, the current sensing
resistors can be calculated. Next, the power MOSFETs and
Schottky diodes are selected. Finally, CIN and COUT are
selected according to the required voltage ripple require-
ments. The circuit on the front page can be confi gured for
operation up to a MOSFET supply voltage of 36V (limited
by the external MOSFETs, VIN capacitor voltage rating and
possibly the minimum on-time).
Operating Frequency and Synchronization
The choice of operating frequency, fOSC, is a trade-off
between effi ciency and component size. Low frequency op-
eration improves effi ciency by reducing MOSFET switching
losses, both gate charge loss and transition loss. However,
lower frequency operation requires more inductance for a
given amount of ripple current. The internal oscillator for
each of the LTC3773’s controllers runs at a nominal 400kHz
frequency when the PLLFLTR pin is left fl oating and the
PLLIN/FC pin input is not switching. Pulling PLLFLTR to
VCC selects 560kHz operation; pulling PLLFLTR to SGND
selects 220kHz operation. Alternatively, the LTC3773 will
phase-lock to a clock signal applied to the PLLIN/FC pin
with a frequency between 160kHz and 700kHz (see Phase-
Locked Loop and Frequency Synchronization).
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is effi ciency. A higher
frequency generally results in lower effi ciency because of
MOSFET gate-charge losses. In addition to this basic trade-
off, the effect of inductor value on ripple current and low
current operation must also be considered. The inductor
value has a direct effect on ripple current. The inductor
ripple current ΔIL decreases with higher inductance or
frequency and increases with higher VIN or VOUT:
IL=VOUT
(f)(L)1– VOUT
VIN
Accepting larger values of ΔIL allows the use of low in-
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔIL = 0.3 to 0.6 (IMAX). Remember, the
maximum ΔIL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET
is on. Burst Mode operation begins when the average
inductor current required results in a peak current below
20% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
higher load currents, which can cause a dip in effi ciency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Actual core loss is independent
of core size for a fi xed inductor value, but it is very de-
pendent on inductance selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper (I2R)
losses will increase.
Ferrite designs have very low core loss and are preferred at
high switching frequencies, so designers can concentrate
on reducing I2R loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and do not radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
APPLICATIONS INFORMATION
LTC3773 Vour VIN VUUT VUUT : M F—*\ “I 1 1 VIN VUUT L7LJCUEN2
LTC3773
16
3773fb
mainly depends on the price vs size requirements and any
radiated fi eld/EMI requirements. New designs for high cur-
rent surface mount inductors are available from numerous
manufacturers, including Coiltronics, Vishay, TDK, Pulse,
Panasonic, Vitec, Coilcraft, Toko and Sumida.
Power MOSFET and Schottky Diode Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
VIN >> VOUT, the top MOSFETs’ on-resistance is normally
less important for overall effi ciency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with signifi cantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by
the driver supply voltage, VDR, requiring the use of logic-
level threshold MOSFETs in most applications. Pay close
attention to the BVDSS specifi cation for the MOSFETs as
well; many of the logic-level MOSFETs are limited to 30V
or less.
Selection criteria for the power MOSFETs include the on-
resistance RDS(ON), input capacitance, input voltage and
maximum output current. MOSFET input capacitance is
a combination of several components but can be taken
from the typical “gate charge” curve included on most data
sheets as shown in Figure 2. The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time. The initial slope is the effect of the
gate-to-source and the gate-to-drain capacitance. The fl at
portion of the curve is the result of the Miller multiplication
effect of the drain-to-gate capacitance as the drain drops the
voltage across the current source load. The upper sloping
line is due to the drain-to-gate accumulation capacitance
and the gate-to-source capacitance.
The Miller charge (the increase in coulombs on the hori-
zontal axis from A to B while the curve is fl at) is specifi ed
for a given VDS drain voltage, but can be adjusted for
different VDS voltages by multiplying by the ratio of the
application VDS to the curve specifi ed VDS values. A way
to estimate the CMILLER term is to take the change in gate
charge from points A and B on a manufacturers data sheet
and divide by the stated VDS voltage specifi ed. CMILLER
is the most important selection criterion for determining
the transition loss term in the top MOSFET but is not di-
rectly specifi ed on MOSFET data sheets. CRSS and COS are
specifi ed sometimes but defi nitions of these parameters
are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT
VIN
Synchronous Switch Duty Cycle =VIN –V
OUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current is given by:
P
MAIN =VOUT
VIN
(IMAX2)(1+)RDS(ON) +
VIN2IMAX
2(RDR )(CMILLER)•
1
VDR –V
TH(IL)
+1
VTH(IL)
(f)
PSYNC =VIN –V
OUT
VIN
(IMAX2)(1+)RDS(ON)
Figure 2. MOSFET Miller Capacitance
APPLICATIONS INFORMATION
MILLER EFFECT
BA
VDS
VGS
VIN
QIN
CMILLER = (QB – QA)/VDS
+
+–
–
+
–
3773 F02
VGS
LTC3773 J VOUTWIN ’ Vow L7 LJUW
LTC3773
17
3773fb
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω
at VGS = VMILLER), and VIN is the drain potential and the
change in drain potential in the particular application.
VTH(IL) is the typical gate threshold voltage shown in the
power MOSFET data sheet at the specifi ed drain current.
CMILLER is the calculated capacitance using the gate charge
curve from the MOSFET data sheet and the technique
described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 12V,
the high current effi ciency generally improves with larger
MOSFETs, while for VIN > 12V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes in Figure 1 conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse recovery period which could
cost as much as several percent in effi ciency. A 2A to 8A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition loss due to
their larger junction capacitance.
CIN and COUT Selection
The selection of CIN is simplifi ed by the 3-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current oc-
curs when only one controller is operating. The controller
with the highest (VOUT)(IOUT) product needs to be used to
determine the maximum RMS capacitor current require-
ment. Increasing the output current drawn from the other
controller will actually decrease the input RMS ripple cur-
rent from its maximum value. The out-of-phase technique
typically reduces the input capacitor’s RMS ripple current
by a factor of 30% to 70% when compared to a single
phase power supply solution.
The type of input capacitor, value and ESR rating have ef-
fi ciency effects that need to be considered in the selection
process. The capacitance value chosen should be suffi cient
to store adequate charge to keep high peak battery currents
down. The ESR of the capacitor is important for capacitor
power dissipation as well as overall battery effi ciency. All
the power (RMS ripple current • ESR) not only heats up
the capacitor but wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramics have
high voltage coeffi cients of capacitance and may have
audible piezoelectric effects; tantalums need to be surge
rated; OS-CONs suffer from higher inductance, larger
case size and limited surface mount applicability; and
electrolytics’ higher ESR and dry out possibility require
several to be used. Sanyo OS-CON SVP, SVPD series; Sanyo
POSCAP TQC series or aluminum electrolytic capacitors
from Panasonic WA series or Cornell Dubilier SPV series,
in parallel with a couple of high performance ceramic ca-
pacitors, can be used as an effective means of achieving
low ESR and large bulk capacitance. Multiphase systems
allow the lowest amount of capacitance overall. As little
as one 22μF or two to three 10μF ceramic capacitors are
an ideal choice in 20W to 35W power supplies due to their
extremely low ESR. Even though the capacitance at 20V
is substantially below their rating at zero-bias, very low
ESR loss makes ceramics an ideal candidate for highest
effi ciency battery operated systems.
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capaci-
tor sized for the maximum RMS current of one channel
must be used. The maximum RMS capacitor current is
given by:
IRMS IOUT(MAX)
VOUT(V
IN –V
OUT )
VIN
APPLICATIONS INFORMATION
LTC3773 L7LJCUEN2
LTC3773
18
3773fb
This formula has a maximum value at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even signifi cant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The benefi t of the LTC3773 multiphase clocking can be
calculated by using the equation above for the highest
power controller and then calculating the loss that would
have resulted if all three channels switched on at the same
time. The total RMS power lost is lower when triple control-
lers are operating due to the interleaving of current pulses
through the input capacitor’s ESR. This is why the input
capacitance requirement calculated above for the worst-
case controller is adequate for the triple controller design.
Remember that input protection fuse resistance, battery
resistance and PC board trace resistance losses are also
reduced due to the reduced peak currents in a multiphase
system. The overall benefi t of a multiphase design will only
be fully realized when the source impedance of the power
supply/battery is included in the effi ciency testing. The
drains of the three top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the drains and CIN may produce undesirable voltage and
current resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfi ed the capacitance is adequate for fi ltering.
The output ripple (ΔVOUT) is determined by:
VOUT ILESR +1
8•f•C
OUT
Where f = operating frequency, COUT = output capacitance,
and ΔIL = ripple current in the inductor. The output ripple is
highest at maximum input voltage since ΔIL increases with
input voltage. With ΔIL = 0.3IOUT(MAX) the output ripple will
typically be less than 50mV at maximum VIN assuming:
COUT Recommended ESR <2RSENSE
and COUT >1
(8 • f • RSENSE)
The fi rst condition relates to the ripple current into
the ESR of the output capacitance while the second
term guarantees that the output capacitance does not
signifi cantly discharge during the operating frequency
period due to ripple current. The choice of using smaller
output capacitance increases the ripple voltage due to the
discharging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
at or below 50mV. The ITH pin OPTI-LOOP compensation
components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.
Manufacturers such as Sanyo, Panasonic and Cornell
Dubilier should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
electrolyte capacitor available from Sanyo has a good
(ESR)(size) product. An additional ceramic capacitor in
parallel with OS-CON capacitors is recommended to offset
the effect of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the relevant ESR or transient
current handling requirements. Aluminum electrolytic
and dry tantalum capacitors are both available in surface
mount confi gurations. New special polymer surface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
output capacitor choices are the Sanyo POSCAP TPD, TPE,
TPF, AVX TPS, TPSV, the Kemet T510 series of surface
mount tantalums, Kemet AO-CAPs or the Panasonic SP
series of surface mount special polymer capacitors avail-
able in case heights ranging from 2mm to 4mm. Other
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturers for other specifi c
recommendations.
RSENSE Selection for Output Current
Once the frequency and inductor have been chosen, RSENSE
is determined based on the required peak inductor current.
The current comparator has a typical maximum threshold
of 75mV/RSENSE and an input common mode range of
SGND to (1.1) • VCC. The current comparator threshold
sets the peak inductor current, yielding a maximum aver-
APPLICATIONS INFORMATION
LTC3773 55mV L7 LJUW
LTC3773
19
3773fb
age output current IMAX equal to the peak value less half
the peak-to-peak ripple current, ΔIL.
Allowing a margin for variations in the IC and external
component values yields:
RSENSE =55mV
IMAX
The IC works well with values of RSENSE from 0.002Ω to
0.1Ω.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
at the maximum duty cycle, with slope compensation, the
maximum inductor peak current is reduced by more than
50%, reducing the maximum output current at high duty
cycle operation. However, the LTC3773’s slope compensa-
tion recovery is implemented to allow 70% rated inductor
peak current at the maximum duty cycle.
VCC and VDR Power Supplies
Power for the top and bottom MOSFET drivers is derived
from the VDR pin; the internal controller circuitry is derived
from the VCC pin. Under typical operating conditions, the
total current consumption at these two pins should be well
below 100mA. Hence, VDR and VCC can be connected to an
external auxiliary 5V power supply. If an auxiliary supply is
not available, a simple zener diode and a darlington NPN
buffer can be used to power these two pins as shown in
Figure 3. To prevent switching noise from coupling to the
sensitive analog control circuitry, VCC should have a 1μF
bypass capacitor, at least, close to the device. The BiCMOS
process that allows the LTC3773 to include large on-chip
MOSFET drivers also limits the maximum VDR and VCC
voltage to 7V. This limits the practical maximum auxiliary
supply to a loosely regulated 7V rail. If VCC drops below
3.9V, LTC3773 goes into undervoltage lockout; if VDR
drops below VCC by more than 1V, the driver outputs are
disabled.
Figure 3. LTC3773 VCC and VDR Power Supplies
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the
BOOST pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in Figure 3 is charged though diode
DB from VDR when the SW pin is low. When the topside
MOSFETs turns on, the driver places the CB voltage across
the gate-source of the desired MOSFET. This enhances
the MOSFET and turns on the topside switch. The switch
node voltage, SW, rises to VIN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply (VBOOST = VDR + VIN). The value of the
boost capacitor CB needs to be 30 to 100 times that of the
total gate charge capacitance of the topside MOSFET(s)
as specifi ed on the manufacturer’s data sheet. The reverse
breakdown of DB must be greater than VIN(MAX).
Regulator Output Voltage
The regulator output voltages are each set by an external
feedback resistive divider carefully placed across the output
capacitor. The resultant feedback signal is compared with
the internal precision 0.6V voltage reference by the error
amplifi er. The output voltage is given by the equation:
VOUT =0.6V 1+R2
R1
where R1 and R2 are defi ned in Figure 1.
+
+
+
+
VOUT
VIN
COUT
CIN
BOOST
TG
SW
BG
VDR
PGND
VCC
LRSENSE
QT
D1
DB
CB
QB
10μF
10μF
0.1μF
0.1μF
10Ω
100Ω
RZ
2k
VZ
6.8V
Q1
LTC3773
3773 F03
Q1: ZETEX FZT603
VZ: ON SEMI MM5Z6V8ST1
SGND
APPLICATIONS INFORMATION
LTC3773 VOUT (i) 0.6V L7LJCUEN2
LTC3773
20
3773fb
SENSE+/SENSE– Pins
The common mode input range of the current compara-
tor sense pins is from 0V to (1.1)VCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.6V to 7.7V, depending upon
the voltage applied to VCC. A differential NPN input stage
is biased with internal resistors from an internal 2.4V
source as shown in Figure 1. This requires that current
either be sourced or sunk from the SENSE pins depending
on the regulator output voltage. If the output voltage is
below 2.4V, current will fl ow out of both SENSE pins to
the main output. The output can be easily preloaded by
the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current fl owing out of each pair of SENSE pins is:
ISENSE
++ISENSE–=2•2.4V – VOUT
60k
Since VFB is servoed to the 0.6V reference voltage, we
can choose R1 in Figure 1 to have a maximum value to
absorb this current.
R1(MAX) =30k 0.6V
2.4V – VOUT
for VOUT <2.4V
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 30k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the VFB
feedback current.
Power Up from Shutdown
If the SDB1, SDB2 and SDB3 pins are forced below 0.4V,
the IC enters low current shutdown mode. Under this
condition, most of the internal circuit blocks, including
the reference, are disabled. The supply current drops to a
typical value of 20μA. Disconnecting the external applied
voltage source allows an internal 0.5μA current source to
pull up the SDBn pin. Once the voltage at any of the SDB
pins is above the shutdown threshold, the reference and
the internal biasing circuit wake up. When the voltage at
the SDBn pin goes above its power-up threshold, its driver
starts to toggle. The power-up thresholds for channels 1, 2
and 3 are set at 1.2V, 1.8V and 2.4V respectively. Adding a
small external capacitor larger than 100pF at the SDB pin
reduces the slew rate at the node, permitting the internal
circuit to settle before actual conversion begins.
LTC3773 can be easily confi gured to produce a sequential
power up/down supply. By adding an external capacitor
at the SDB pin; or by controlling the SDB input voltage,
channel 1 will be powered up fi rst, followed by channel
2 and sequentially channel 3. The channel turn on time
delay is determined by the SDB capacitor value. Figure 4
shows the sequential power up/down confi guration and
its waveform. The capacitor at the TRACK pins control
the individual channel power up slew rate.
Soft-Start/Tracking
When the voltage on the TRACK pin is less than the
internal 0.6V reference, the LTC3773 regulates the VFB
voltage to the TRACK pin voltage instead of 0.6V. After
the soft-start/tracking cycle, the TRACK pin voltage must
be higher than 0.8V; otherwise, the tracking circuit intro-
duces offset in the error amplifi er and the switcher output
will be regulated to a slightly lower potential. If tracking is
not required, a soft-start capacitor should be connected
to the TRACK pin to regulate the output startup slew rate.
SDB1
SDB2
SDB3
TRACK1
TRACK2
TRACK3
LTC3773
RAMP
SOURCE
POWER
DOWN
0V TO 2V
CSLEW
1MΩCSS
10k
2.5V VOUT1 1V/DIV
1.8V VOUT2 1V/DIV
1.2V VOUT3 1V/DIV
SDB
1V/DIV
0.1s/DIV 3773 F04
Figure 4. Sequential Power Up/Down
APPLICATIONS INFORMATION
LTC3773 \x é‘fii. o|__|___ N i fl LN Mm. HEJ
LTC3773
21
3773fb
VFB1
TRACK2
TRACK3
TRACK1
VFB2
VFB3
LTC3773
VOUT1
VOUT2
VOUT3
R12
R11
R22
R21
R32
R31
R22
R21
R32
R31
3773 F05b
1MΩ
CSS
MASTER
VOUT
R12
R11
10k
CSLEW
RAMP
SOURCE
TRACK
DOWN
0V TO 2V
2.5V VOUT1 1V/DIV
1.8V VOUT2 1V/DIV
1.2V VOUT3 1V/DIV
TRACK 1
1V/DIV
0.1s/DIV 3773 F05b
Figure 5a. Ratiometric Tracking. TRACK1 Functions
as a Soft-Start Pin; VOUT2 and VOUT3 Track VOUT1
with Ratiometric Start-Up Slew Rate
Figure 5b. Coincident Tracking. TRACK1 Functions
as a Soft-Start Pin; VOUT2 and VOUT3 Track VOUT1
with the Same Start-Up Slew Rate
VFB1
TRACK2
TRACK3
TRACK1
VFB2
VFB3
LTC3773
VOUT1
1MΩ
CSS
VOUT2
VOUT3
R12
R11
MASTER
VOUT
RM2
RM1
R22
R21
R32
R31
10k
3773 F04a
CSLEW
RAMP
SOURCE
TRACK
DOWN
0V TO 2V
2.5V VOUT1 1V/DIV
1.8V VOUT2 1V/DIV
1.2V VOUT3 1V/DIV
TRACK 1
0.5V/DIV
0.1s/DIV 3773 F05a
An internal 1μA current source pull-up at the TRACK pin
programs the output to take about 600ms/μF to reach its
steady state value. The output voltage ramp down slew
rate can be controlled by the external capacitor CSLEW
and the TRACK DOWN switch as shown in Figure 5a
and 5b.
With a simple confi guration, TRACK allows VOUT start-
up to track the master channel as shown qualitatively
in Figures 5a and 5b. The LTC3773 can be confi gured
for two different up/down tracking modes:coincident or
ratiometric.
To implement the ratiometric tracking shown in Figure 5a,
no extra divider is needed; simply connect the TRACK2
and TRACK3 pins to the TRACK1 pin. Do not connect
TRACK to the VFB pin. With a ratiometric confi guration,
the LTC3773 produces three different output slew rates.
Because each channel’s slew rate is proportional to its
corresponding output voltage, the three output voltages
reach their steady-state values at about the same time.
If any of the channel SDB pins are asserted, its TRACK
pin will be internally pulled low and all channels will be
disabled.
To implement coincident tracking, connect extra resistor
dividers to the output of channel 1. These resistor dividers
are selected to be the same as the VFB dividers across
the outputs of channels 2 and 3. TRACK2 and TRACK3
are connected to these extra resistor dividers as shown
in Figure 5b. In this tracking scheme, VOUT1 must be set
higher than VOUT2 and VOUT3. The coincident confi gura-
tion produces the same slew rate at the three outputs,
so that the lowest output voltage channel reaches its
steady state fi rst.
The TRACK pin 1μA internal pull-up current performs the
soft-start action, but in tracking mode it introduces an
error term in the resistive divider. To minimize this error,
build the resistive divider with smaller value resistors, or
APPLICATIONS INFORMATION
LTC3773 L7LJCUEN2
LTC3773
22
3773fb
add an extra tracking resistive divider. When the tracking
resistive divider input is grounded, the pull-up current fl ow-
ing through the network could produce a small unwanted
offset at the TRACK pin, forcing the controller to create
an unwanted low voltage supply at the regulator output.
To compensate for this error, the LTC3773 introduces a
30mV offset in the tracking circuit, which disables the
driver until the potential at the TRACK pin is above 30mV.
The magnitude of this offset diminishes as the potential
at the TRACK pin approaches 100mV, allowing accurate
tracking after startup.
Fault Conditions: Current Limit and Current Foldback
The LTC3773 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET cur-
rent of 75mV/RSENSE. The maximum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3773 includes current foldback to help further
limit load current when the output is shorted to ground.
If the potential at the TRACK pin is above 0.54V and the
VFB voltage falls below 70% of its nominal level, then the
maximum sense voltage is progressively lowered from
75mV to 15mV. Under short-circuit conditions with very
low duty cycles, the LTC3773 will begin cycle skipping in
order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time, tON(MIN),
of the LTC3773 (less than 200ns), the input voltage and
inductor value:
IL(SC) = tON(MIN)
VIN
L
The resulting short-circuit current is:
ISC =15mV
RSENSE
1
2IL(SC)
Disable Current Foldback at Start-Up
At start-up, if the potential at the TRACK pin is lower than
0.54V, the LTC3773 current comparator threshold voltage
stays at 75mV and the regulator current limit remains at
its rated value. This feature allows the LTC3773 to power
the core and I/O of low voltage FPGAs.
When power is fi rst applied to an FPGA, the device can
draw current several times its normal operating current.
This power-on surge current is due to the programmable
nature of FPGAs. When the FPGA powers up, before ini-
tialization, the RAM cells are briefl y in a random state. This
results in contention at the interconnect and signifi cant
power dissipation. The duration of the power-on surge
current is typically quite brief but can cause problems
for power supply designs. LTC3773 views currents that
are outside the normal operation range as possible short-
circuits. Disabling the current foldback at startup allows
the regulator to provides a higher surge current to meet
the FPGA’s requirement. Nevertheless, when calculating
the current sense resistor value for FPGA power supply
applications, the computed output current value must be
higher than the power-on surge current to allow a proper
startup.
Fault Conditions: Overvoltage Protection
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage
faults greater than 3.75% above the nominal output volt-
age. When this condition is sensed, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared. The bottom MOSFET
remains on continuously for as long as the OV condition
persists. If VOUT returns to a safe level, normal operation
automatically resumes.
Note that under extreme power-up conditions, e.g. with
high input voltage, a small inductor and a small soft-start
capacitor, once the OV comparator trips, the output volt-
age might continue to charge above the rated value until
the energy in the inductor is depleted. The peak of the
overshoot might be higher than the rated voltage of the
output capacitors.
Phase-Locked Loop and Frequency Synchronization
The LTC3773 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external N channel
APPLICATIONS INFORMATION
LTC3773 «4000 ”H L7 LJUW
LTC3773
23
3773fb
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the PLLFLTR pin. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the oscillators
are identical. At the stable operating point, the phase
detector has high impedance and the fi lter capacitor CLP
holds the voltage.
The loop fi lter components, CLP and RLP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The fi lter
components CLP and RLP determine how fast the loop ac-
quires lock. Typically RLP = 10k and CLP is 0.01μF to 0.1μF.
The external clock (on the PLLIN/FC pin) input threshold
is typically 1V. Table 2 summarizes the different states in
which the PLLIN/FC and PLLFLTR pins can be used.
Table 2. PLLFLTR Pin Voltage vs Switching Frequency
PLLFLTR PLLIN/FC FREQUENCY
GND DC Voltage 220kHz
Floating DC Voltage 400kHz
V
CC DC Voltage 560kHz
RC Loop Filter Clock Signal Phase-Locked
to External Clock
Figure 6b. Relationship Between Oscillator Frequency
and Voltage at the PLLFLTR Pin When Synchronizing
to an External Clock
VPLLFLTR (V)
0 0.5 1 1.5 2 2.5 3.0
SYNCHRONIZATION SWITCHING FREQUENCY (kHz)
800
3773 F06b
700
400
500
600
300
200
100
VCC = 5V
Figure 6a. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR OSCILLATOR
VCC
RLP
CLP
3773 F06a
PLLFLTR
EXTERNAL
OSCILLATOR
PLLIN/
FC
APPLICATIONS INFORMATION
MOSFET of controller 1 to be locked to the rising edge of
an external clock signal applied to the PLLIN/FC pin. The
turn-on of controller 2’s/3’s external N-channel MOSFET
and CLKOUT signal are controlled by the PHASEMD
pin as showed in Table 1. Note that when PHASEMD is
forced high, controller 2 and controller 3 outputs can be
connected in parallel to produce a higher output power
voltage source.
Table 1. Phase Relationship between the PLLIN/FC Pin vs
Controller 1, 2, 3 Top Gate and CLKOUT Pin
PHASEMD CH1 CH2 CH3 CLKOUT
GND 0 Deg 120 Deg 240 Deg 60 Deg
Floating 0 Deg 120 Deg 240 Deg 0 Deg
V
CC 0 Deg 90 Deg 270 Deg 180 Deg
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
A simplifi ed Phase-Locked Loop Block Diagram is shown
in Figure 6a. The output of the phase detector is a pair of
complementary current sources that charge or discharge
the external fi lter network connected to the PLLFLTR pin.
The relationship between the voltage on the PLLFLTR pin
and operating frequency, when there is a clock signal ap-
plied to PLLIN/FC, is shown in Figure 6b and specifi ed in
the Electrical Characteristics table. Note that the LTC3773
can only be synchronized to an external clock whose
frequency is within range of the LTC3773’s internal VCO,
which is nominally 160kHz to 700Hz. This is guaranteed,
over temperature and variations, to be between 200kHz
and 540kHz.
LTC3773 VOUT L7LJCUEN2
LTC3773
24
3773fb
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCC
VCC
RPLLFL2
CLP
3773 F07
PLLFLTR
RPLLFL1
PHASE
DETECTOR/
OSCILLATOR
PLLIN/FC
BG1
CLKOUT
OSCILLATOR
Figure 7. Fixed Frequency Adjustment
The LTC3773 can be confi gured to operate at any switch-
ing frequency within the synchronization range. Figure 7
shows a simple circuit to achieve this. The resistive divider
at the PLLFLTR pin programs the LTC3773 switching
frequency according to the transfer curve of Figure 6b. By
connecting the PLLIN/FC pin to the BG1 or the CLKOUT
(UHF package only) node, the pre-set frequency selection
is disengaged and the PLLFLTR pin potential determines
the switching frequency.
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a signifi cant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that is low enough in
value to provide suffi cient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of IOUT(MAX) at VIN(MAX).
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD • ESR, where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time, VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior, but also provides a DC coupled and
AC fi ltered closed-loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON(MIN) <VOUT
VIN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the IC is generally about
130ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of par-
ticular concern in forced continuous applications with low
APPLICATIONS INFORMATION
LTC3773 VOUT Vow 1.8V 1.8V L7 LJUW
LTC3773
25
3773fb
The ITH series RC-CC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
to maximize transient response once the fi nal PC layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
decided upon because the various types and values deter-
mine the loop feedback factor gain and phase. An output
current pulse of 20% to 80% of full load current having
a rise time of <2μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
output voltage step, resulting from the step change in
output current, may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the fi ltered
and compensated control loop response. The gain of the
loop will be increased by increasing RC and the bandwidth
of the loop will be increased by decreasing CC. If RC is
increased by the same factor that CC is decreased, the
zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
For a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Application Note 76.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automobile
is the source of a number of nasty potential transients, in-
cluding load dump, reverse battery and double battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the fi eld collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators fi nding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 8 is the most straightforward
approach to protect a DC/DC converter from the ravages
of an automotive battery line. The series diode prevents
current from fl owing during reverse battery, while the
transient suppressor clamps the input voltage during
load dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the IC has a maximum input voltage of 36V on
the SW pins, most applications will be limited to 30V by
the MOSFET BVDSS.
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 15A, and
f = 220kHz.
The inductance value is chosen fi rst based on a 30%
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Short the
PLLFLTR pin to ground to program for 220kHz operation.
The minimum inductance for 30% ripple current is:
L=VOUT
(f)(IL)1– VOUT
VIN
=1.8V
(220k)(30%)(15A)11.8V
22V
=1.67μH
Using L = 1.5μH, a commonly available value results in
30% ripple current. The peak inductor current will be the
maximum DC value plus one half the ripple current, or
17.3A. Increasing the ripple current will also help ensure
APPLICATIONS INFORMATION
LTC3773
+
3773 F08
VCC
5V VBAT
12V
TG
SW
BG
PGND
Figure 8. Automotive Application Protection
LTC3773 VOUT 15V 15mV 1 130ns(22V) VIM ) 511 55mV 0.6V 0.6V E E ; i 22v 1.8V L7LJCUEN2
LTC3773
26
3773fb
that the minimum on-time of 130ns is not violated. The
minimum on-time occurs at maximum VIN:
tON(MIN) =VOUT
VIN
(
MAX
)
f=1.8V
22V(220kHz) =372ns
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specifi cation with a con-
servative maximum sense current threshold of 55mV:
RSENSE 55mV
17.3A3.2m
Use a commonly available 0.003Ω sense resistor.
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output voltage
but also to absorb the SENSE pin’s specifi ed input current.
R1(MAX) =30k 0.6V
2.4V VOUT
=30k 0.6V
2.4V 1.8V
=30k
Choosing 1% resistors; R1 = 10k and R2 = 20k yields an
output voltage of 1.8V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Renesas HAT2168H MOSFET
results in: RDS(ON) = 13.5mΩ, CMILLER = 6nC/25V = 240pF.
At maximum input voltage with T (estimated) = 50°C:
PMAIN=1.8V
22V (15)21+(0.005)(50°C25°C)
[]
(13.5m)
+(22V)215A
2
(2)(240pF)
1
51.8 +1
1.8
(220kHz)
=0.612W
Using a Renesas HAT2165H as a bottom MOSFET, the
worst-case power dissipation by the synchronous MOSFET
under normal operating conditions at elevated ambient
temperature and an estimated 50°C junction temperature
rise is:
PSYNC =22V 1.8V
22V (15)2(1.125)(5.3m)=1.23W
A short-circuit to ground will result in a folded back
current of
ISC =15mV
0.0031
2
130ns(22V)
1.5μH
=4.05A
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Check the following in the
PC layout:
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN? Do
not attempt to split the input decoupling for the three
channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? Keep
the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under
the IC. The SGND pin should be used to hook up all
control circuitry on one side of the IC. The combined
LTC3773 SGND pin and the ground return of CVCC must
return to the combined COUT (–) terminals. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the charge pump circuitry. The path formed by
the top N-channel MOSFET, Schottky diode and the CIN
capacitor should have short leads and PC trace lengths.
The power ground returns to the sources of the bottom
N-channel MOSFETs, anodes of the Schottky diodes
and (–) plates of CIN, which should have as short lead
lengths as possible.
3. The VCC decoupling capacitor should be placed immedi-
ately adjacent to the IC between the VCC pin and SGND.
A 1μF ceramic capacitor of the X7R type is small enough
to fi t very close to the IC to minimize the ill effects of the
large current pulses drawn to drive the bottom MOSFETs.
An additional 4.7μF to 10μF of ceramic, tantalum or other
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
4. Do the LTC3773 VFB resistive dividers connect to the (+)
terminals of COUT? The resistive divider must be con-
APPLICATIONS INFORMATION
LTC3773 L7 LJUW
LTC3773
27
3773fb
nected between the (+) terminal of COUT and SGND and
a small decoupling capacitor should be placed across
this divider; as close as possible to the LTC3773 SGND
pin and away from any high current or high frequency
switching nodes.
5. Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The fi lter capacitors between SENSE+ and
SENSE– for each channel should be as close as possible
to the pins of the IC. Connect the SENSE– and SENSE+
pins to the pads of the sense resistor as illustrated in
Figure 9.
6. Keep the switching nodes, SW, BOOST and TG away
from sensitive small-signal nodes (SENSE+, SENSE–,
VFB, ITH). Ideally the SW, BOOST and TG printed circuit
traces should be routed away and separated from the IC
and the “quiet” side of the IC. Separate the high dV/dt
printed circuit traces from sensitive small-signal nodes
with ground traces or ground planes.
7. Use a low impedance source such as a logic gate to
drive the PLLIN pin and keep the lead as short as
possible.
8. Minimize trace impedances of TG, BG and SW nets.
TG and SW must be routed in parallel with minimum
distance.
Figure 10 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after study-
ing the current waveforms why it is critical to keep the
high switching current paths to a small physical size.
High electric and magnetic fi elds will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal
of the input capacitor and not share a common ground
path with any switched current paths. The left half of the
circuit gives rise to the “noise” generated by a switching
regulator. The ground terminations of the synchronous
MOSFETs and Schottky diodes should return to the bot-
tom plate(s) of the input capacitor(s) with a short isolated
PC trace since very high switched currents are present.
A separate isolated path from the bottom plate(s) of the
input and output capacitor(s) should be used to tie in the IC
power ground pin (PGND). This technique keeps inherent
signals generated by high current pulses taking alternate
current paths that have fi nite impedances during the total
period of the switching regulator. External OPTI-LOOP
compensation allows overcompensation for PC layouts
which are not optimized but this is not the recommended
design procedure.
APPLICATIONS INFORMATION
LTC3773
SENSE+
SENSE–
INDUCTOR
OUTPUT
CAPACITOR
1000pF
10Ω
37773 F09
SENSE
RESISTOR
10Ω
Figure 9. Kelvin Sensing RSENSE
LTC3773 L7LJCUEN2
LTC3773
28
3773fb
Figure 10. Branch Current Waveforms
RL1
L1
SW1 VOUT1
COUT1
+
VIN
RSENSE1
RSENSE2
RSENSE3
CIN
RIN +
RL3
BOLD LINES INDICATE
HIGH SWITCHING
CURRENTS.
KEEP LINES TO A
MINIMUM LENGTH.
L3
SW3
3773 F10
VOUT3
COUT3
+
D2 RL2
L2
SW2 VOUT2
COUT2
+
D1
D3
APPLICATIONS INFORMATION
LTC3773 Flu ‘sanF L7 LJUW
LTC3773
29
3773fb
Figure 11. 3-Phase, Dual Output with Coincident Output Tracking Function
TRACK1
VFB1
ITH1
SGND
ITH2
ITH3
VFB2
VFB3
TRACK2
TRACK3
SENSE2–
SENSE2+
BOOST1
TG1
SW1
SW2
TG2
BOOST2
BOOST3
TG3
SW3
BG1
BG2
VDR
PGND
SDB3
SDB2
SDB1
SENSE1–
SENSE1+
PHASEMD
PGOOD
SENSE3–
SENSE3+
VCC
PLLFLTR
PLLIN/FC
CLKOUT
BG3
1
2
3
4
5
6
7
8
9
10
11
12
31
30
29
28
27
26
25
24
23
22
21
20
0.01μF
1500pF
1500pF
VOUT1
VOUT2
15k
47.5k
6.8k
10k
20k
10k
10Ω
10Ω
10k
10k
20k
39 38 37 36 35 34 33 32
13 14 15 16 17 18 19
PGOOD
POWER DOWN VOUT1
POWER DOWN VOUT2
0.1μF
1nF
0.1μF
47μF
47μF
x2
0.1μF
0.1μF
CMDSH-3
CMDSH-3
CMDSH-3
HAT2168H
HAT2168H
HAT2165H
HAT2165H
HAT2168H
HAT2165H
VIN
VIN
4.5V TO 22V
V5V
4.5V TO 6V
VIN
B340B
B340B
B340B
L1
1μH
L2
0.6μH
CIN
56μF
25V
x5
L3
0.6μH
+
+
10μF
+
COUT1
330μF
4V
x2
10μF
25V
x6
COUT2
330μF
2.5V
x4
+
LTC3773
3mΩ
3mΩ
3mΩ
CLKOUT
CLKIN
CONTINUOUS
MODE FOR
TRACKING
L1: PULSE PG0006.102
L2, L3: PULSE PG0006.601
COUT1: SANYO POSCAP 4TPD330M
COUT2: SANYO POSCAP 2R5TPE330M9
10Ω
10Ω
10Ω
10Ω
1nF
15k
1μF10μF
+
VOUT1
2.5V/15A
VOUT2
1.8V/30A
3773 F11
2Ω
330pF
100pF
1nF
APPLICATIONS INFORMATION
lIC3773 IDDDDDDDDDDDDDDDDDD¢ T Lflflflflflflflflflflflflflflflflmfl QH‘i a e 5007550‘ 0093025 9‘ L; T IZSUrVSIU‘ C) flflflflflflflflflflflflflflflflflfl’ I 7407820 HHHHHHHHHHHHHHHHHHAAJ w» UZZ’DSB W 055 i 0L5 L7LJCUEN2
LTC3773
30
3773fb
G36 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 14 15 16 17 1813
12.50 – 13.10*
(.492 – .516)
2526 22 21 20 19232427282930313233343536
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
PACKAGE DESCRIPTION
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
LTC3773 —[Uflflflmflfiflfl[fl AlflflflflflLj WE l a fiaflflmw 31+ r; 1 *1 #‘e 1 8 // ¢ 0 i W I MLU/ i T iii fl? UUUUUiUUUUU‘U Wmmmflmm S 3 42 fig 3 3 JL g4; W L7 LJUW
LTC3773
31
3773fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
How-
ever, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
0.40 ± 0.10
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
(UH) QFN 0205
0.50 BSC
0.200 REF
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
3.15 ± 0.10
(2 SIDES)
0.40 ±0.10
0.00 – 0.05
0.75 ± 0.05
0.70 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
3.15 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
5.50 ± 0.05
(2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
LTC3773 L7LJCUEN2
LTC3773
32
3773fb
SENSE2+
SENSE2–
TRACK3
TRACK2
VFB3
VFB2
ITH3
ITH2
SGND
LTC3773
ITH1
VFB1
TRACK1
PGOOD
10k
10Ω
10Ω
PGND
SDB3
VDR
BG2
BG1
SW3
TG3
BOOST3
BOOST2
TG2
SW2
SW1
TG1
BOOST1
39
POWER DOWN VOUT1
L1:
TDK RLF7030T-2R2M5R4
L2, L3:
TDK RLF7030T-1R5M5R4
COUT1 COUT2 COUT3,:
SANYO POSCAP 4TPE220MF
POWER DOWN VOUT2
POWER DOWN VOUT3
SDB2
38
SDB1
37
SENSE1–
36
SENSE1+
35
1000pF
PHASEMD
34
PGOOD
SENSE3–
SENSE3+
VCC
PLLFLTR
PLLIN/FC
CLKOUT
BG3
33 32
13 14 15 16 17 18 19
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
+
3773 TA02
1
8 Si4816BDY
22μF
X5R
0.1μF
0.1μF
CMDSH-3
CMDSH-3
CMDSH-3
0.1μF
VIN
4.5V TO 14V
47μF
16V
COUT1
220μF
4V
VOUT1
3.3V/5A
7mΩ
L1
2.2μH
5
4
2, 3
6, 7
+
4.7μF
4.7μF
16V
+
+
1
8 Si4816BDY
22μF
X5R
VIN
4.7μF
16V
COUT2
220μF
4V
VOUT2
2.5V/5A
7mΩ
L2
1.5μH
5
4
2, 3
6, 7
+
1
8 Si4816BDY
22μF
X5R
VIN
4.7μF
16V
COUT3
220μF
4V
VOUT3
1.8V/5A
7mΩ
L3
1.5μH
5
4
2, 3
6, 7
+
10k
20k
20k
10Ω10Ω10Ω10Ω
10Ω
31.6k
8.2k
5.9k
10k
0.01μF
1nF
0.01μF
150pF
150pF
150pF
1nF
1nF
1000pF
1000pF
68.1k
0.01μF
2.2μF0.1μF
15k
VCC
4.5V TO 6V
TYPICAL APPLICATION
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0907 REV B • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC3407-2 Dual Synchronous, 800mA, 2.25MHz Step-Down Monolithic
DC/DC Regulator
VIN: 2.5V to 5.5V, VOUT: 0.6V to 5V, 100% Maximum Duty Cycle
LTC3417A Dual Synchronous Step-Down Monolithic 1.5A/1A VIN: 2.25V to 5.5V, VOUT: 0.8V to 5V, 100% Maximum Duty Cycle
LTC3703 High Input Synchronous Step-Down Controller VIN ≤ 100V
LTC3708 No RSENSETM
, Dual, 2-Phase Synchronous Step-Down Controller
with Output Tracking
Very Low Duty Factor Operation, Programmable Output Voltage
Voltage Up/Down Tracking
LTC3727 Dual Output 2-Phase Current Mode Synchronous DC/DC Step-
Down Switching Regulator Controller
VIN: 4V to 36V, VOUT: 0.8V to 14V, 99% Maximum Duty Cycle,
Selectable Burst Mode Operation
LTC3728 Dual PolyPhase® Synchronous Step-Down Switching Regulator Dual Output, Current Mode
LTC3729 20A to 200A, 500kHz PolyPhase Synchronous Controller Expandable from 2-Phase, Uses All Surface Mount Components,
VIN up to 36V
LTC3731 3- to 12-Phase Step-Down Synchronous Controller Single Output, 60A to 240A Output Current, 0.6V ≤ VOUT ≤ 6V,
4.5V ≤ VIN ≤ 32V
LTC3778 Wide Operating Range, No RSENSE Step-Down Controller Single Channel, Separate VON Programming
LTC3802 Dual PolyPhase Voltage Mode Synchronous Step-Down
Switching Regulator with Output Tracking
Very Low Duty Factor Operation, Programmable Output Voltage
Up/Down Tracking, VIN Up to 30V
LTC3827 Low IQ, Dual, 2-Phase Synchronous Step-Down Controller Low 80μA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V
No RSENSE is a trademark of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation.
RELATED PARTS
Figure 12. High Effi ciency, Small Footprint Triple Output Step-Down Converter