TLC227x(A)-Q1 Datasheet by Texas Instruments

U Ordering & Technical Design & o o quahiy documentation development I TEXAS INSTRUMENTS 3 Support & (raming 16 \ TA = 25"c \O=150uA ‘0 : :500 DD:
TLC227x-Q1 Advanced, Rail-To-Rail, LinCMOS™ Operational Amplifiers
1 Features
• AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to 125°C, TA
•Functional Safety-Capable
–Documentation available to aid functional safety
system design (TLC2272-Q1)
–Documentation available to aid functional safety
system design (TLC2272A-Q1)
• Output swing includes both supply rails
• Low noise: 9 nV/√Hz typical at f = 1 kHz
• Low input bias current: 1 pA typical
• Fully specified for both single-supply and split-
supply operation
• Common-mode input voltage range includes
negative rail
• High-gain bandwidth: 2.2 MHz typical
• High slew rate: 3.6 V/μs typical
• Low input offset voltage: 950 μV maximum at
TA = 25°C
• Macromodel included
2 Applications
•Body control module
•Battery management system
•Car audio
•DC/DC converter
•Electric power steering
•Engine control unit
•Gasoline engine
•Instrument clusters
•Inverter and motor control
•On-board charger
•Telematics control unit
•Transmission control
•White goods (refrigerators, washing machines)
3 Description
The TLC227x-Q1 are dual and quad, LinCMOS™
operational amplifiers. Both devices exhibit rail-to-rail
output performance for increased dynamic range in
single- or split-supply applications. The TLC227x-Q1
family offers 2 MHz of bandwidth and 3 V/μs of slew
rate for higher-speed applications. These devices
offer comparable ac performance while having better
noise, input offset voltage, and power dissipation than
existing CMOS op amps. The TLC227x‑Q1 has a
noise voltage of 9 nV/√Hz—two times lower than
competitive solutions.
The TLC227x-Q1, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. In addition, the rail-to-rail
output feature, with single- or split-supplies, makes
this family a great choice when interfacing with
analog-to-digital converters (ADCs).
For precision applications, the TLC227xA-Q1 family
is available with a maximum input offset voltage of
950 μV. This family is fully characterized at 5 V and
±5 V.
These devices offer increased output dynamic range,
lower noise voltage, and lower input offset voltage.
This enhanced feature set allows the TLC227x-Q1
to be used in a wider range of applications. For
applications that require higher output drive and
wider input voltage range, see the TLV2432-Q1 and
TLV2442-Q1. All the parameters of the TLC227x-Q1
family enables these devices to be applicable in most
automotive applications.
Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TLC2272-Q1,
TLC2272A-Q1
SOIC (8) 4.90 mm x 3.91 mm
TSSOP (8) 3.00 mm × 4.40 mm
TLC2274-Q1,
TLC2274A-Q1
SOIC (14) 8.65 mm x 3.91 mm
TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
|VDD ±| − Supply Voltage (V)
10
8
6
4
12
14
16
TA= 25°C
IO= ± 50 µA
IO= ± 500 µA
V(OPP) − Maximum Peak-to-Peak Output Voltage (V)VO(PP)
46 8 10 12 14 16
Maximum Peak-To-Peak Output Voltage
vs Supply Voltage
TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1
SGLS007G – FEBRUARY 2003 – REVISED AUGUST 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: VDD = 5 V (TLC2272-
Q1 and TLC2272A-Q1)................................................. 5
6.6 Electrical Characteristics: VDD± = ±5 V
(TLC2272-Q1 and TLC2272A-Q1)................................6
6.7 Electrical Characteristics: VDD = 5 V (TLC2274-
Q1 and TLC2274A-Q1)................................................. 8
6.8 Electrical Characteristics: VDD± = ±5 V
(TLC2274-Q1 and TLC2274A-Q1)................................9
6.9 Typical Characteristics.............................................. 11
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................22
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 24
8.3 Power Supply Recommendations.............................26
8.4 Layout....................................................................... 26
9 Device and Documentation Support............................27
9.1 Device Support......................................................... 27
9.2 Documentation Support............................................ 27
9.3 Receiving Notification of Documentation Updates....27
9.4 Support Resources................................................... 27
9.5 Trademarks...............................................................27
9.6 Electrostatic Discharge Caution................................28
9.7 Glossary....................................................................28
10 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2016) to Revision G (August 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added functional safety information to Features bullets.....................................................................................1
Changes from Revision E (January 2012) to Revision F (March 2016) Page
• Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layoutsection, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............ 1
• Added ESD ratings table.................................................................................................................................... 4
Changes from Revision D (March 2009) to Revision E (January 2012) Page
• Deleted ESD ratings table.................................................................................................................................. 4
TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1
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TEXAS INSTRUMENTS 1OUT [I U a JVDm 10UT[1 U14]4OUT 1|Nr[ 2 7 ]2OUT 1|N—[ 2 ‘3]4w7 1|N+[ a 6]2|N— 1|N+[ 3 12]4\N+ VDDJGNDI: 4 5 ]2|N+ VDD,[ A n JVDD, 2|N+[ 5 10]3\N+ 2|N—[ e 9]3\N7 20UT[ 7 5]30UT
5 Pin Configuration and Functions
Figure 5-1. TLC2272-Q1 and TLC2272A-Q1:
D (8‑Pin SOIC) or PW (8‑Pin TSSOP)
Packages, Top View
Figure 5-2. TLC2274-Q1 and TLC2274A-Q1:
D (14‑Pin SOIC) or PW (14‑Pin TSSOP)
Packages, Top View
Table 5-1. Pin Functions
PIN
TYPE DESCRIPTION
NAME
NO.
TLC2272-Q1,
TLC2272A-Q1
TLC2274-Q1,
TLC2274A-Q1
1IN+ 3 3 Input Noninverting input, channel 1
1IN– 2 2 Input Inverting input, channel 1
1OUT 1 1 Output Output, channel 1
2IN+ 5 5 Input Noninverting input, channel 2
2IN– 6 6 Input Inverting input, channel 2
2OUT 7 7 Ouput Output, channel 2
3IN+ — 10 Input Noninverting input, channel 3
3IN– — 9 Input Inverting input, channel 3
3OUT — 8 Output Output, channel 3
4IN+ — 12 Input Noninverting input, channel 4
4IN– — 13 Input Inverting input, channel 4
4OUT — 14 Output Output, channel 4
VDD+ 8 4 Input Positive (highest) supply
VDD– 4 11 Input Negative (lowest) supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VDD+(2) 8 V
VDD–(2) –8 V
Differential input voltage, VID (3) ±16 V
Input voltage, VI(any input)(2) VDD− − 0.3 VDD+ V
Input current, II (any input) ±5 mA
Output current, IO±50 mA
Total current into VDD+ ±50 mA
Total current out of VDD– ±50 mA
Duration of short-circuit current at (or below) 25°C(4) Unlimited
Operating free-air temperature range, TA–40 125 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or PW package 260 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD−.
(3) Differential voltages are at IN+ with respect to IN–. Excessive current will flow if input is brought below VDD– − 0.3 V.
(4) The output can be shorted to either supply. Temperature or supply voltages must be limited so that the maximum dissipation rating is
not exceeded.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2 ±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD± Supply voltage ±2.2 ±8 V
VIInput voltage VDD− VDD+ −1.5 V
VIC Common-mode input voltage VDD− VDD+ −1.5 V
TAOperating free-air temperature −40 125 °C
TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1
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6.4 Thermal Information
THERMAL METRIC(1)
TLC2272-Q1, TLC2272A-Q1 TLC2274-Q1, TLC2274A-Q1
UNITD (SOIC) PW (TSSOP) D (SOIC) PW (TSSOP)
8 PINS 8 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 115.6 175.8 83.8 111.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.8 58.8 43.2 41.2 °C/W
RθJB Junction-to-board thermal resistance 55.9 104.3 38.4 54.7 °C/W
ψJT Junction-to-top characterization parameter 14.3 5.9 9.4 3.9 °C/W
ψJB Junction-to-board characterization parameter 55.4 102.3 38.1 53.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: VDD = 5 V (TLC2272-Q1 and TLC2272A-Q1)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
TLC2272-Q1 TA = 25°C 300 2500
µV
TLC2272A-Q1 300 950
TLC2272-Q1 Full Range(1) 3000
TLC2272A-Q1 1500
αVIO Temperature coefficient of
input offset voltage VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω 2 μV/°C
Input offset voltage long-term drift(2) VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω 0.002 μV/mo
IIO Input offset current VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω TA = 25°C 0.5 60 pA
Full Range(1) 800
IIB Input bias current VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω TA = 25°C 1 60 pA
Full Range(1) 800
VICR Common-mode input voltage RS = 50 Ω; |VIO | ≤ 5 mV TA = 25°C –0.3 2.5 4 V
Full Range(1) 0 2.5 3.5
VOH High-level output voltage
IOH = −20 μA 4.99
V
IOH = −200 μA TA = 25°C 4.85 4.93
Full Range(1) 4.85
IOH = −1 mA TA = 25°C 4.25 4.65
Full Range(1) 4.25
VOL Low-level output voltage VIC = 2.5 V
IOL = 50 μA 0.01
V
IOL = 500 μA TA = 25°C 0.09 0.15
Full Range(1) 0.15
IOL = 5 mA TA = 25°C 0.9 1.5
Full Range(1) 1.5
AVD Large-signal differential
voltage amplification VIC = 2.5 V, VO = 1 V to 4 V RL = 10 kΩ(3) TA = 25°C 10 35
V/mVFull Range(1) 10
RL = 1 MΩ(3) 175
rid Differential input resistance 1012 Ω
riCommon-mode input resistance 1012 Ω
ciCommon-mode input capacitance f = 10 kHz, P package 8 pF
zoClosed-loop output impedance f = 1 MHz, AV = 10 140 Ω
CMRR Common-mode rejection ratio VIC = 0 V to 2.7 V, VO = 2.5 V, RS = 50 Ω TA = 25°C 70 75 dB
Full Range(1) 70
kSVR Supply-voltage rejection ratio
(ΔVDD / ΔVIO)VDD = 4.4 V to 16 V, VIC = VDD / 2, no load TA = 25°C 80 95 dB
Full Range(1) 80
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6.5 Electrical Characteristics: VDD = 5 V (TLC2272-Q1 and TLC2272A-Q1) (continued)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Supply current VO = 2.5 V, no load TA = 25°C 2.2 3 mA
Full Range(1) 3
SR Slew rate at unity gain VO = 0.5 V to 2.5 V, RL = 10 kΩ(3),
CL = 100 pF(3)
TA = 25°C 2.3 3.6 V/µs
Full Range(1) 1.7
VnEquivalent input noise voltage f = 10 Hz 50 nV/√Hz
f = 1 kHz 9
VNPP Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz 1 µV
f = 0.1 Hz to 10 Hz 1.4
InEquivalent input noise current 0.6 fA/√Hz
THD+N Total harmonic distortion + noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 10 kΩ(3)
AV = 1 0.0013%
AV = 10 0.004%
AV = 100 0.03%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ(3), CL = 100 pF(3) 2.18 MHz
BOM Maximum output-swing bandwidth VO(PP) = 2 V, AV = 1, RL = 10 kΩ(3), CL = 100 pF(3) 1 MHz
tsSettling time AV = –1, RL = 10 kΩ(3),
Step = 0.5 V to 2.5 V, CL = 100 pF(3)
To 0.1% 1.5 µs
To 0.01% 2.6
φmPhase margin at unity gain RL = 10 kΩ(3), CL = 100 pF(3) 50°
Gain margin RL = 10 kΩ(3), CL = 100 pF(3) 10 dB
(1) TA = –40°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(3) Referenced to 0 V.
6.6 Electrical Characteristics: VDD± = ±5 V (TLC2272-Q1 and TLC2272A-Q1)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VIC = 0 V, VO = 0 V,
RS = 50 Ω
TLC2272-Q1 TA = 25°C 300 2500
µV
TLC2272A-Q1 300 950
TLC2272-Q1 Full Range(1) 3000
TLC2272A-Q1 1500
αVIO Temperature coefficient of
input offset voltage VIC = 0 V, VO = 0 V, RS = 50 Ω 2 μV/°C
Input offset voltage long-term drift(2) VIC = 0 V, VO = 0 V, RS = 50 Ω 0.002 μV/mo
IIO Input offset current VIC = 0 V, VO = 0 V, RS = 50 Ω TA = 25°C 0.5 60 pA
Full Range(1) 800
IIB Input bias current VIC = 0 V, VO = 0 V, RS = 50 Ω TA = 25°C 1 60 pA
Full Range(1) 800
VICR Common-mode input voltage RS = 50 Ω; |VIO | ≤ 5 mV TA = 25°C –5.3 0 4 V
Full Range(1) –5 0 3.5
VOM+ Maximum positive peak
output voltage
IO = −20 μA 4.99
V
IO = −200 μA TA = 25°C 4.85 4.93
Full Range(1) 4.85
IO = −1 mA TA = 25°C 4.25 4.65
Full Range(1) 4.25
VOM- Maximum negative
peak output voltage VIC = 0 V
IO = 50 μA –4.99
V
IO = 500 μA TA = 25°C –4.85 –4.91
Full Range(1) –4.85
IO = 5 mA TA = 25°C –3.5 –4.1
Full Range(1) –3.5
TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1
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6.6 Electrical Characteristics: VDD± = ±5 V (TLC2272-Q1 and TLC2272A-Q1) (continued)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVD Large-signal differential
voltage amplification VO = ±4 V RL = 10 kΩ TA = 25°C 20 50
V/mVFull Range(1) 20
RL = 1 MΩ 300
rid Differential input resistance 1012 Ω
riCommon-mode input resistance 1012 Ω
ciCommon-mode input capacitance f = 10 kHz, P package 8 pF
zoClosed-loop output impedance f = 1 MHz, AV = 10 130 Ω
CMRR Common-mode rejection ratio VIC = –5 V to 2.7 V, VO = 0 V, RS = 50 Ω TA = 25°C 75 80 dB
Full Range(1) 75
kSVR Supply-voltage rejection ratio
(ΔVDD / ΔVIO)VDD+ = 2.2 V to ±8 V, VIC = 0 V, no load TA = 25°C 80 95 dB
Full Range(1) 80
IDD Supply current VO = 0 V, no load TA = 25°C 2.4 3 mA
Full Range(1) 3
SR Slew rate at unity gain VO = ±2.3 V, RL = 10 kΩ, CL = 100 pF TA = 25°C 2.3 3.6 V/µs
Full Range(1) 1.7
VnEquivalent input noise voltage f = 10 Hz 50 nV/√Hz
f = 1 kHz 9
VNPP Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz 1 µV
f = 0.1 Hz to 10 Hz 1.4
InEquivalent input noise current 0.6 fA/√Hz
THD+N Total harmonic distortion + noise VO = ±2.3, f = 20 kHz, RL = 10 kΩ
AV = 1 0.0011%
AV = 10 0.004%
AV = 100 0.03%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ, CL = 100 pF 2.25 MHz
BOM Maximum output-swing bandwidth VO(PP) = 4.6 V, AV = 1, RL = 10 kΩ, CL = 100 pF 0.54 MHz
tsSettling time AV = –1, RL = 10 kΩ,
Step = –2.3 V to 2.3 V, CL = 100 pF
To 0.1% 1.5 µs
To 0.01% 3.2
φmPhase margin at unity gain RL = 10 kΩ, CL = 100 pF 52°
Gain margin RL = 10 kΩ, CL = 100 pF 10 dB
(1) TA = –40°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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6.7 Electrical Characteristics: VDD = 5 V (TLC2274-Q1 and TLC2274A-Q1)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
TLC2274-Q1 TA = 25°C 300 2500
µV
TLC2274A-Q1 300 950
TLC2274-Q1 Full Range(1) 3000
TLC2274A-Q1 1500
αVIO Temperature coefficient of
input offset voltage VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω 2 μV/°C
Input offset voltage long-term drift(2) VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω 0.002 μV/mo
IIO Input offset current VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω TA = 25°C 0.5 60 pA
Full Range(1) 800
IIB Input bias current VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω TA = 25°C 1 60 pA
Full Range(1) 800
VICR Common-mode input voltage RS = 50 Ω; |VIO | ≤ 5 mV TA = 25°C –0.3 2.5 4 V
Full Range(1) 0 2.5 3.5
VOH High-level output voltage
IOH = −20 μA 4.99
V
IOH = −200 μA TA = 25°C 4.85 4.93
Full Range(1) 4.85
IOH = −1 mA TA = 25°C 4.25 4.65
Full Range(1) 4.25
VOL Low-level output voltage VIC = 2.5 V
IOL = 50 μA 0.01
V
IOL = 500 μA TA = 25°C 0.09 0.15
Full Range(1) 0.15
IOL = 5 mA TA = 25°C 0.9 1.5
Full Range(1) 1.5
AVD Large-signal differential
voltage amplification VIC = 2.5 V, VO = 1 V to 4 V RL = 10 kΩ(3) TA = 25°C 10 35
V/mVFull Range(1) 10
RL = 1 MΩ(3) 175
rid Differential input resistance 1012 Ω
riCommon-mode input resistance 1012 Ω
ciCommon-mode input capacitance f = 10 kHz, P package 8 pF
zoClosed-loop output impedance f = 1 MHz, AV = 10 140 Ω
CMRR Common-mode rejection ratio VIC = 0 V to 2.7 V, VO = 2.5 V, RS = 50 Ω TA = 25°C 70 75 dB
Full Range(1) 70
kSVR Supply-voltage rejection ratio
(ΔVDD / ΔVIO)VDD = 4.4 V to 16 V, VIC = VDD / 2, no load TA = 25°C 80 95 dB
Full Range(1) 80
IDD Supply current VO = 2.5 V, no load TA = 25°C 4.4 6 mA
Full Range(1) 6
SR Slew rate at unity gain VO = 0.5 V to 2.5 V,
RL = 10 kΩ(3), CL = 100 pF(3)
TA = 25°C 2.3 3.6 V/µs
Full Range(1) 1.7
VnEquivalent input noise voltage f = 10 Hz 50 nV/√Hz
f = 1 kHz 9
VNPP Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz 1 µV
f = 0.1 Hz to 10 Hz 1.4
InEquivalent input noise current 0.6 fA/√Hz
THD+N Total harmonic distortion + noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 10 kΩ(3)
AV = 1 0.0013%
AV = 10 0.004%
AV = 100 0.03%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ(3), CL = 100 pF(3) 2.18 MHz
BOM Maximum output-swing bandwidth VO(PP) = 2 V, AV = 1, RL = 10 kΩ(3), CL = 100 pF(3) 1 MHz
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6.7 Electrical Characteristics: VDD = 5 V (TLC2274-Q1 and TLC2274A-Q1) (continued)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tsSettling time AV = –1, RL = 10 kΩ(3),
Step = 0.5 V to 2.5 V, CL = 100 pF(3)
To 0.1% 1.5 µs
To 0.01% 2.6
φmPhase margin at unity gain RL = 10 kΩ(3), CL = 100 pF(3) 50°
Gain margin RL = 10 kΩ(3), CL = 100 pF(3) 10 dB
(1) TA = –40°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(3) Referenced to 0 V.
6.8 Electrical Characteristics: VDD± = ±5 V (TLC2274-Q1 and TLC2274A-Q1)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VIC = 0 V, VO = 0 V,
RS = 50 Ω
TLC2274-Q1 TA = 25°C 300 2500
µV
TLC2274A-Q1 300 950
TLC2274-Q1 Full Range(1) 3000
TLC2274A-Q1 1500
αVIO Temperature coefficient of
input offset voltage VIC = 0 V, VO = 0 V, RS = 50 Ω 2 μV/°C
Input offset voltage long-term drift(2) VIC = 0 V, VO = 0 V, RS = 50 Ω 0.002 μV/mo
IIO Input offset current VIC = 0 V, VO = 0 V, RS = 50 Ω TA = 25°C 0.5 60 pA
Full Range(1) 800
IIB Input bias current VIC = 0 V, VO = 0 V, RS = 50 Ω TA = 25°C 1 60 pA
Full Range(1) 800
VICR Common-mode input voltage RS = 50 Ω; |VIO | ≤ 5 mV TA = 25°C –5.3 0 4 V
Full Range(1) –5 0 3.5
VOM+ Maximum positive peak
output voltage
IO = −20 μA 4.99
V
IO = −200 μA TA = 25°C 4.85 4.93
Full Range(1) 4.85
IO = −1 mA TA = 25°C 4.25 4.65
Full Range(1) 4.25
VOM- Maximum negative peak
output voltage VIC = 0 V
IO = 50 μA –4.99
V
IO = 500 μA TA = 25°C –4.85 –4.91
Full Range(1) –4.85
IO = 5 mA TA = 25°C –3.5 –4.1
Full Range(1) –3.5
AVD Large-signal differential
voltage amplification VO = ±4 V RL = 10 kΩ TA = 25°C 20 50
V/mVFull Range(1) 20
RL = 1 MΩ 300
rid Differential input resistance 1012 Ω
riCommon-mode input resistance 1012 Ω
ciCommon-mode input capacitance f = 10 kHz, P package 8 pF
zoClosed-loop output impedance f = 1 MHz, AV = 10 130 Ω
CMRR Common-mode rejection ratio VIC = –5 V to 2.7 V, VO = 0 V, RS = 50 Ω TA = 25°C 75 80 dB
Full Range(1) 75
kSVR Supply-voltage rejection ratio
(ΔVDD / ΔVIO)VDD+ = 2.2 V to ±8 V, VIC = 0 V, no load TA = 25°C 80 95 dB
Full Range(1) 80
IDD Supply current VO = 0 V, no load TA = 25°C 4.8 6 mA
Full Range(1) 6
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6.8 Electrical Characteristics: VDD± = ±5 V (TLC2274-Q1 and TLC2274A-Q1) (continued)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR Slew rate at unity gain VO = ±2.3 V, RL = 10 kΩ, CL = 100 pF TA = 25°C 2.3 3.6 V/µs
Full Range(1) 1.7
VnEquivalent input noise voltage f = 10 Hz 50 nV/√Hz
f = 1 kHz 9
VNPP Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz 1 µV
f = 0.1 Hz to 10 Hz 1.4
InEquivalent input noise current 0.6 fA/√Hz
THD+N Total harmonic distortion + noise VO = ±2.3, f = 20 kHz, RL = 10 kΩ
AV = 1 0.0011%
AV = 10 0.004%
AV = 100 0.03%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ, CL = 100 pF 2.25 MHz
BOM Maximum output-swing bandwidth VO(PP) = 4.6 V, AV = 1, RL = 10 kΩ, CL = 100 pF 0.54 MHz
tsSettling time AV = –1, RL = 10 kΩ,
Step = –2.3 V to 2.3 V, CL = 100 pF
To 0.1% 1.5 µs
To 0.01% 3.2
φmPhase margin at unity gain RL = 10 kΩ, CL = 100 pF 52°
Gain margin RL = 10 kΩ, CL = 100 pF 10 dB
(1) TA = –40°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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6.9 Typical Characteristics
Table 6-1. Table of Graphs
FIGURE(1)
VIO Input offset voltage Distribution 1, 2, 3, 4
vs Common-mode voltage 5, 6
αVIO Input offset voltage temperature coefficient Distribution 7, 8, 9, 10 (2)
IIB /IIO Input bias and input offset current vs Free-air temperature 11 (2)
VIInput voltage vs Supply voltage 12
vs Free-air temperature 13 (2)
VOH High-level output voltage vs High-level output current 14 (2)
VOL Low-level output voltage vs Low-level output current 15, 16 (2)
VOM+ Maximum positive peak output voltage vs Output current 17 (2)
VOM- Maximum negative peak output voltage vs Output current 18 (2)
VO(PP) Maximum peak-to-peak output voltage vs Frequency 19
IOS Short-circuit output current vs Supply voltage 20
vs Free-air temperature 21 (2)
VOOutput voltage vs Differential input voltage 22, 23
AVD
Large-signal differential voltage amplification vs Load resistance 24
Large-signal differential voltage amplification and phase margin vs Frequency 25, 26
Large-signal differential voltage amplification vs Free-air temperature 27 (2), 28 (2)
z0Output impedance vs Frequency 29, 30
CMRR Common-mode rejection ratio vs Frequency 31
vs Free-air temperature 32
kSVR Supply-voltage rejection ratio vs Frequency 33, 34
vs Free-air temperature 35 (2)
IDD Supply current vs Supply voltage 36 (2), 37 (2)
vs Free-air temperature 38 (2), 39 (2)
SR Slew rate vs Load Capacitance 40
vs Free-air temperature 41 (2)
VO
Inverting large-signal pulse response 42, 43
Voltage-follower large-signal pulse response 44, 45
Inverting small-signal pulse response 46, 47
Voltage-follower small-signal pulse response 48, 49
VnEquivalent input noise voltage vs Frequency 50, 51
Noise voltage over a 10-second period 52
Integrated noise voltage vs Frequency 53
THD+N Total harmonic distortion + noise vs Frequency 54
Gain-bandwidth product vs Supply voltage 55
vs Free-air temperature 56 (2)
φmPhase margin vs Load capacitance 57
Gain margin vs Load capacitance 58
(1) For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
(2) Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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6.9 Typical Characteristics (continued)
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
10
5
0
20
15
−1.6 −1.2 0 0.4 0.8 1.2 1.6
891 Amplifiers From
−0.8 − 0.4
2 Wafer Lots
VDD =±2.5 V
TA= 25°C
Figure 6-1. Distribution of TLC2272-Q1 Input Offset Voltage
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
10
5
0
20
15
−1.6 −1.2 0 0.4 0.8 1.2 1.6
−0.8 − 0.4
891 Amplifiers From
2 Wafer Lots
VDD =±5 V
TA= 25°C
Figure 6-2. Distribution of TLC2272-Q1 Input Offset Voltage
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
10
5
0
20
15
0 0.4 0.8 1.2 1.6
992 Amplifiers From
−1.6 − 1.2 −0.8 −0.4
2 Wafer Lots
VDD =±2.5 V
Figure 6-3. Distribution of TLC2274-Q1 Input Offset Voltage
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
10
5
0
20
15
0 0.4 0.8 1.2 1.6
992 Amplifiers From
−1.6 − 1.2 −0.8 −0.4
2 Wafer Lots
VDD =±5 V
Figure 6-4. Distribution of TLC2274-Q1 Input Offset Voltage
0.5
0
−1
−1 0 1
VIO − Input Offset Voltage − mV
1
2 3 4 5
VIO
VIC − Common-Mode Voltage − V
VDD = 5 V
TA= 25°C
RS= 50 Ω
−0.5
Figure 6-5. Input Offset Voltage vs Common-Mode Voltage
0.5
0
−1
−1 0 1
VIO − Input Offset Voltage − mV
1
2345
VIC − Common-Mode Voltage − V
VIO
−0.5
VDD =±5 V
TA= 25°C
RS= 50 Ω
−6 −5 −4 − 3 −2
Figure 6-6. Input Offset Voltage vs Common-Mode Voltage
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6.9 Typical Characteristics (continued)
15
10
5
0
−1 0 1
Percentage of Amplifiers − %
20
25
2 3 4 5
αVIO − Temperature Coefficient − µ °V/ C
128 Amplifiers From
2 Wafer Lots
VDD =±2.5 V
P Package
25°C to 125°C
−5 − 4 −3 −2
Figure 6-7. Distribution of TLC2272-Q1 vs Input Offset Voltage
Temperature Coefficient
−5 − 4 −3 −2
15
10
5
0
−1 0 1
Percentage of Amplifiers − %
20
25
2 3 4 5
αVIO − Temperature Coefficient − µ °V/ C
128 Amplifiers From
2 Wafer Lots
VDD =±5 V
P Package
25°C to 125°C
Figure 6-8. Distribution of TLC2272-Q1 vs Input Offset Voltage
Temperature Coefficient
15
10
5
0
0 1
Percentage of Amplifiers − %
20
25
2 3 4 5
αVIO − Temperature Coefficient − µ °V/ C
−5 − 4 −3 − 2 −1
128 Amplifiers From
2 Wafer Lots
VDD =±2.5 V
N Package
TA= 25°C to 125°C
Figure 6-9. Distribution of TLC2274-Q1 vs Input Offset Voltage
Temperature Coefficient
15
10
5
0
Percentage of Amplifiers − %
20
25
αVIO − Temperature Coefficient − µ °V/ C
012345
−5 − 4 −3 − 2 −1
128 Amplifiers From
2 Wafer Lots
VDD =±2.5 V
N Package
TA= 25°C to 125°C
Figure 6-10. Distribution of TLC2274-Q1 vs Input Offset Voltage
Temperature Coefficient
15
10
5
0
25 45 65 85
20
25
30
105 125
TA− Free-Air Temperature − °C
35
VDD =±2.5 V
VIC = 0 V
VO= 0 V
RS= 50 Ω
IIB
IIO
IIB and IIO − Input Bias and Input Offset Currents − pA
IB
IIIO
Figure 6-11. Input Bias and Input Offset Current vs Free-Air
Temperature
Figure 6-12. Input Voltage vs Supply Voltage
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6.9 Typical Characteristics (continued)
−75 − 25 0 25 50 75 100 125
2
1
0
−1
3
4
5
− Input Voltage − V
VI
TA− Free-Air Temperature − °C
|VIO|≤5 mV
VDD = 5 V
− 50
Figure 6-13. Input Voltage vs Free-Air Temperature
V0H − High-Level Output Voltage − V
VOH
IOH − High-Level Output Current − mA
4
2
1
0
6
3
0 1 2 3 4
5
VDD = 5 V
TA= 125°C
TA= − 55°C
TA= 25°C
Figure 6-14. High-Level Output Voltage vs High-Level Output
Current
VOL − Low-Level Output Voltage − V
0.6
0.4
0.2
0
0 1 2 3
0.8
4 5
VDD = 5 V
TA= 25°C
IOL − Low-Level Output Current − mA
VOL
VIC = 1.25 V
1
1.2
VIC = 2.5 V
VIC = 0 V
Figure 6-15. Low-Level Output Voltage vs Low-Level Output
Current
VOL − Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
VOL
0.6
0.4
0.2
0
0 1 2 3
0.8
4
1
1.2
5 6
1.4 VDD = 5 V
VIC = 2.5 V
TA= 125°C
TA= 25°C
TA= − 55°C
Figure 6-16. Low-Level Output Voltage vs Low-Level Output
Current
3
2
1
0 1 2 3 4 5
− Maximum Positive Peak Output Voltage − V
4
5
|IO| − Output Current − mA
TA= − 55°C
TA= 25°C
TA= 125°C
VDD ±=±5 V
VOM +
Figure 6-17. Maximum Positive Peak Output Voltage vs Output
Current
0 1 2 3 4 5 6
IO− Output Current − mA
VDD =±5 V
VIC = 0 V
TA= 125°C
TA= 25°C
TA= − 55°C
−3.8
−4
−4.2
−4.4
−4.6
−4.8
−5
− Maximum Negative Peak Output Voltage − V
VOM −
Figure 6-18. Maximum Positive Peak Output Voltage vs Output
Current
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l TEXAS INSTRUMENTS VDD : W I v“, = .m m ,4 /K Wu ‘ / TA VID V‘D m
6.9 Typical Characteristics (continued)
2
1
0
10 k 100 k 1 M
3
f − Frequency − Hz
4
10 M
6
5
7
8
9
10
V(OPP) − Maximum Peak-to-Peak Output Voltage − V
VO(PP)
VDD = 5 V
VDD =±5 V
RL= 10 kΩ
TA= 25°C
Figure 6-19. Maximum Peak-to-Peak Output Voltage vs
Frequency
4
0
2 3 4
8
12
16
5 6 7 8
IOS − Short-Circuit Output Current − mA
OS
I
|VDD ±| − Supply Voltage − V
VID = 100 mV
VO= 0 V
TA= 25°C
−8
VID = − 100 mV
−4
Figure 6-20. Short-Circuit Output Current vs Supply Voltage
−5
−75 − 50 − 25 0 25 50 75 100 125
−1
−3
7
11
15
IOS − Short-Circuit Output Current − mA
OS
I
TA− Free-Air Temperature − °C
VID = 100 mV
VID = − 100 mV
VO= 0 V
VDD =±5 V
Figure 6-21. Short-Circuit Output Current vs Free-Air
Temperature
3
2
1
0
800
4
5
1200
VID − Differential Input Voltage − µV
− Output Voltage − V
VO
−800 − 400 4000
VDD = 5 V
TA= 25°C
RL= 10 kΩ
VIC = 2.5 V
Figure 6-22. Output Voltage vs Differential Input Voltage
1
−1
−3
−5
0 250
3
5
500 750 1000
VID − Differential Input Voltage − µV
− Output Voltage − V
VO
−1000 −750 −250−500
VDD =±5 V
TA= 25°C
RL= 10 kΩ
VIC = 0 V
Figure 6-23. Output Voltage vs Differential Input Voltage
0.1
1
0.1 1 10 100
10
100
1000
RL− Load Resistance − kΩ
VO=±1 V
TA= 25°C
VDD =±5 V
VDD = 5 V
AVD − Large-Signal Differential
AVD
Voltage Amplification − dB
Figure 6-24. Large-Signal Differential Voltage Amplification vs
Load Resistance
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TEXAS INSTRUMENTS wm J TA VA A\l
6.9 Typical Characteristics (continued)
0
20
1 k 10 k 100 k 1 M
40
60
80
f − Frequency − Hz
10 M
om − Phase Margin
φm
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
−20
−40 − 90°
−45°
0°
45°
90°
135°
180°
AVD − Large-Signal Differential
AVD
Voltage Amplification − dB
Figure 6-25. Large-Signal Differential Voltage Amplification and
Phase Margin vs Frequency
0
20
1 k 10 k 100 k 1 M
40
60
80
f − Frequency − Hz
10 M
VDD =±5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
om − Phase Margin
φm
−20
−40 − 90°
−45°
0°
45°
90°
135°
180°
AVD − Large-Signal Differential
AVD
Voltage Amplification − dB
Figure 6-26. Large-Signal Differential Voltage Amplification and
Phase Margin vs Frequency
−75 − 50 − 25 0 25 50 75 100 125
10
100
1 k
TA− Free-Air Temperature − °C
VDD = 5 V
VIC = 2.5 V
VO= 1 V to 4 V
RL= 1 MΩ
RL= 10 kΩ
AVD − Large-Signal Differential
AVD
Voltage Amplification − V/mV
Figure 6-27. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
−75 − 50 − 25 0 25 50 75 100 125
10
100
1 k
TA− Free-Air Temperature − °C
RL= 1 MΩ
RL= 10 kΩ
VDD =±5 V
VIC = 0 V
VO=±4 V
AVD − Large-Signal Differential
AVD
Voltage Amplification − V/mV
Figure 6-28. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
10
1
0.1
1000
100
100 1 k 10 k 100 k 1 M
zo − Output Impedance − O
f − Frequency − Hz
Ω
zo
VDD = 5 V
TA= 25°C
AV= 100
AV= 10
AV= 1
Figure 6-29. Output Impedance vs Frequency
10
1
0.1
1000
100
100 1 k 10 k 100 k 1 M
zo − Output Impedance − O
f − Frequency − Hz
Ω
zo
VDD =±5 V
TA= 25°C
AV= 100
AV= 10
AV= 1
Figure 6-30. Output Impedance vs Frequency
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l TEXAS INSTRUMENTS TA ksvx. VA \ M 1 \\ VDD:
6.9 Typical Characteristics (continued)
60
40
20
0
10 100 1 k 10 k
CMRR − Common-Mode Rejection Ratio − dB
80
100
100 k 1 M
f − Frequency − Hz
VDD =±5 V
VDD = 5 V
10 M
TA= 25°C
Figure 6-31. Common-Mode Rejection Ratio vs Frequency
TA− Free-Air Temperature − °C
CMRR − Common-Mode Rejection Ratio − dB
82
78
74
70
86
90
−75 −50 −25 0 25 50 75 100 125
VDD =±5 V
VDD = 5 V
VIC = 0 V to 2.7 V
VIC = −5 V to 2.7 V
Figure 6-32. Common-Mode Rejection Ratio vs Free-Air
Temperature
40
20
0
10 100 1 k
kSVR − Supply-Voltage Rejection Ratio − dB
60
80
f − Frequency − Hz
100
10 k 100 k 1 M 10 M
kSVR
VDD = 5 V
TA= 25°C
kSVR+
kSVR −
−20
Figure 6-33. Supply-Voltage Rejection Ratio vs Frequency
40
20
0
10 100 1 k
kSVR − Supply-Voltage Rejection Ratio − dB
60
80
f − Frequency − Hz
100
10 k 100 k 1 M 10 M
kSVR
VDD =±5 V
TA= 25°C
kSVR+
kSVR −
−20
Figure 6-34. Supply-Voltage Rejection Ratio vs Frequency
kSVR − Supply Voltage Rejection Ratio − dB
kSVR
TA− Free-Air Temperature − °C
−75 − 50 −25 0 25 50 75 100 125
100
95
90
85
105
110
VDD ±=±2.2 V to ±8 V
VO= 0 V
Figure 6-35. Supply-Voltage Rejection Ratio vs Free-Air
Temperature
0 1 2 3 4 5 6 7 8
0
0.6
1.2
1.8
2.4
3
IDD − Supply Current − mA
DD
I
|VDD ±| − Supply Voltage − V
VO= 0 V
No Load
TA= 25°C
TA= − 55°C
TA= 125°C
Figure 6-36. TLC2272-Q1 Supply Current vs Supply Voltage
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I TEXAS INSTRUMENTS \ \\\ Vim: YA 1,; ~ L \ SR— TA
6.9 Typical Characteristics (continued)
0 1 2 3 4 5 6 7 8
0
1.2
2.4
3.6
4.8
6
IDD − Supply Current − mA
DD
I
|VDD ±| − Supply Voltage − V
VO= 0 V
No Load
TA= 25°C
TA= − 55°C
TA= 125°C
Figure 6-37. TLC2274-Q1 Supply Current vs Supply Voltage
−75 − 50 − 25 0 25 50 75 100 125
0
0.6
1.2
1.8
2.4
3
TA− Free-Air Temperature − °C
IDD − Supply Current − mA
DD
I
VDD = 5 V
VO= 2.5 V
VDD =±5 V
VO= 0 V
Figure 6-38. TLC2272-Q1 Supply Current vs Free-Air
Temperature
−75 − 50 −25 0 25 50 75 100 125
0
1.2
2.4
3.6
4.8
6
TA− Free-Air Temperature − °C
IDD − Supply Current − mA
DD
I
VDD = 5 V
VO= 2.5 V
VDD =±5 V
VO= 0 V
Figure 6-39. TLC2274-Q1 Supply Current vs Free-Air
Temperature
µs
SR − Slew Rate − V/
0
1
2
3
CL− Load Capacitance − pF
10 k1 k10010
SR +
SR −
4
5
VDD = 5 V
AV= − 1
TA= 25°C
Figure 6-40. Slew Rate vs Load Capacitance
3
2
1
4
µs
SR − Slew Rate − V/
−75 − 50 − 25 0 25 50 75 100 125
TA− Free-Air Temperature − °C
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
AV= 1
SR +
SR −
0
5
Figure 6-41. Slew Rate vs Free-Air Temperature
2
1
0
1 2 3 4 5
3
4
5
6 7 8 9
VO − Output Voltage − mV
VO
t − Time − µs
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= − 1
0
Figure 6-42. Inverting Large-Signal Pulse Response
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i E INSTRU MENTS
6.9 Typical Characteristics (continued)
0
− 1
− 3
− 4
− 5
4
− 2
12345
2
1
3
5
6 7 8 9
VO − Output Voltage − V
VO
t − Time − µs
VDD =±5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= − 1
0
Figure 6-43. Inverting Large-Signal Pulse Response
3
2
1
0
1 2 3 4 5
4
5
6 7 8 9
VO − Output Voltage − V
VO
t − Time − µs
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
AV= 1
TA= 25°C
0
Figure 6-44. Voltage-Follower Large-Signal Pulse Response
0
−1
4
12345
2
1
3
5
6789
VO − Output Voltage − V
VO
t − Time − µs
VDD =±5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= 1
0
−2
−3
−5
−4
Figure 6-45. Voltage-Follower Large-Signal Pulse Response
2.5
2.45
2.4
0.5 1 1.5 2 2.5
2.55
2.6
2.65
3.5 4.5 5 5.5
VO − Output Voltage − V
VO
t − Time − µs
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= −1
034
Figure 6-46. Inverting Small-Signal Pulse Response
0
−100
0 0.5 1 1.5 2
50
100
2.5 3 3.5 4
VO − Output Voltage − mV
VO
t − Time − µs
VDD =±5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= 1
−50
Figure 6-47. Inverting Small-Signal Pulse Response
2.5
2.45
2.4
2.55
2.6
0 0.5 1 1.5
VO − Output Voltage − V
VO
t − Time − µs
2.65
VDD = 5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= 1
Figure 6-48. Voltage-Follower Small-Signal Pulse Response
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I TEXAS INSTRUMENTS humps
6.9 Typical Characteristics (continued)
0
−50
−100
50
100
0 0.5 1 1.5
VO − Output Voltage − mV
VO
t − Time − µs
VDD =±5 V
RL= 10 kΩ
CL= 100 pF
TA= 25°C
AV= 1
Figure 6-49. Voltage-Follower Small-Signal Pulse Response
20
10
0
10 100 1 k
Vn − Equivalent Input Noise Voltage − nV Hz
30
f − Frequency − Hz
40
10 k
60
VnnV/ Hz
VDD = 5 V
TA= 25°C
RS= 20 Ω
Figure 6-50. Equivalent Input Noise Voltage vs Frequency
20
10
0
10 100 1 k
Vn − Equivalent Input Noise Voltage − nV Hz
30
f − Frequency − Hz
40
10 k
60
VnnV/ Hz
VDD =±5 V
TA= 25°C
RS= 20 Ω
Figure 6-51. Equivalent Input Noise Voltage vs Frequency
−750
−1000
2 4 6
0
250
8 10
Noise Voltage − nV
t − Time − s
0
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA= 25°C
500
750
1000
−250
−500
Figure 6-52. Noise Voltage Over a 10 Second Period
Integrated Noise Voltage − uVRMS
1
0.1
100
1 10 100 1 k
f − Frequency − Hz
10 k 100 k
VRMS
µ
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA= 25°C
10
Figure 6-53. Integrated Noise Voltage vs Frequency
0.0001
0.001
100 1 k 10 k 100 k
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
0.01
0.1
1
VDD = 5 V
TA= 25°C
RL= 10 kΩ
AV= 100
AV= 10
AV= 1
Figure 6-54. Total Harmonic Distortion + Noise vs Frequency
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I TEXAS INSTRUMENTS VDD: TA ‘ HHHH fa WW 7 Rmm‘Wn \ H / \ HHH \ -3 M, \——1" \‘—- . ”1 R “WEN; _ ‘ HHH \ \ L L
6.9 Typical Characteristics (continued)
Gain-Bandwidth Product − MHz
2.1
2
0 1 2 3 4 5
2.2
2.3
6 7 8
|VDD ±| − Supply Voltage − V
2.4
2.5
f = 10 kHz
RL= 10 kΩ
CL= 100 pF
TA= 25°C
Figure 6-55. Gain-Bandwidth Product vs Supply Voltage
−75 − 50 − 25 0 25 50 75 100 125
TA− Free-Air Temperature − °C
Gain-Bandwidth Product − MHz
1.8
1.6
1.4
2
2.4
2.2
2.6
2.8
3
VDD = 5 V
f = 10 kHz
RL= 10 kΩ
CL= 100 pF
Figure 6-56. Gain-Bandwidth Product vs Free-Air Temperature
10
om − Phase Margin
10000
CL− Load Capacitance − pF
φm
1000100
VDD =±5 V
TA= 25°C
Rnull = 20 Ω
Rnull = 10 Ω
Rnull = 0
75°
60°
45°
30°
15°
0°
10 kΩ
10 kΩ
VDD −
VDD +
Rnull
CL
VI
Rnull = 100 Ω
Rnull = 50 Ω
Figure 6-57. Phase Margin vs Load Capacitance
3
0
10
Gain Margin − dB
6
9
10000
CL− Load Capacitance − pF
12
15
1000100
VDD = 5 V
AV= 1
RL= 10 kΩ
TA= 25°C
Figure 6-58. Gain Margin vs Load Capacitance
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7 Detailed Description
7.1 Overview
The TLC227x-Q1 devices are a rail-to-rail output operational amplifiers. These devices operate from a 4.4-V to
16-V single supply and a ±2.2-V ±8-V dual supply, are unity-gain stable, and are an excellent choice for a wide
range of general-purpose applications.
7.2 Functional Block Diagram
Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
VDD +
IN +
IN −
R3 R4 R1 R2
OUT
VDD−
Table 7-1. Actual Device Component Count(1)
COMPONENT TLC2272-Q1 TLC2274-Q1
Transistors 38 76
Resistors 26 52
Diodes 9 18
Capacitors 3 6
(1) Includes both amplifiers and all ESD, bias, and trim circuitry.
7.3 Feature Description
The TLC227x-Q1 family features 2-MHz bandwidth and voltage noise of 9 nV/√Hz with performance rated from
4.4 V to 16 V across an automotive temperature range (–40°C to +125°C). LinMOS is a great choice for a wide
range of audio, automotive, industrial, and instrumentation applications.
7.4 Device Functional Modes
The TLC227x-Q1 family of devices is powered on when the supply is connected. The device can operate with
single or dual supply, depending on the application. The device is in full performance after the supply is greater
than the recommended value.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Macromodel Information
Macromodel information provided was derived using MicroSim Parts, the model generation software used with
PSpice®. The Boyle macromodel (see also Section 9.2.1) and subcircuit in Figure 8-1 were generated using the
TLC227x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−+
−
+−
.SUBCKT TLC227x 1 2 3 4 5
C1 11 1214E−12
C2 6 760.00E−12
DC 5 53DX
DE 54 5DX
DLP 90 91DX
DLN 92 90DX
DP 4 3DX
EGND 99 0POLY (2) (3,0) (4,) 0 .5 .5
FB 99 0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA 6 011 12 377.0E−6
GCM 0 6 10 99 134E−9
ISS 3 10DC 216.OE−6
HLIM 90 0VLIM 1K
J1 11 210 JX
J2 12 110 JX
R2 6 9100.OE3
RD1 60 112.653E3
RD2 60 122.653E3
R01 8 550
R02 7 9950
RP 3 44.310E3
RSS 10 99925.9E3
VAD 60 4−.5
VB 9 0DC 0
VC 3 53 DC .78
VE 54 4DC .78
VLIM 7 8DC 0
VLP 91 0DC 1.9
VLN 0 92DC 9.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
VCC +
RP
IN −
2
IN+
1
VCC −
VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5
RO1
RO2
HLIM
90
DIP
91
DIN
92
VINVIP
99
7
Figure 8-1. Boyle Macromodels and Subcircuit
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I TEXAS INSTRUMENTS T m V0 if V0 if
8.2 Typical Application
_
+
RS
V1V2
VBAT
R1
VOUT
ILOAD
ILOUD
R2
0.1 µF R
Rg
47 kΩ
Figure 8-2. High-Side Current Monitor Equivalent Schematic (Each Amplifier)
8.2.1 Design Requirements
For this design example, use these parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
PARAMETER VALUE
VBAT Battery voltage 12 V
RSENSE Sense resistor 0.1 Ω
ILOAD Load current 0 A to 10 A
Operational amplifier Set in differential configuration with gain = 10
8.2.2 Detailed Design Procedure
This circuit is designed for measuring the high-side current in automotive body control modules with a 12-V
battery or similar applications. The operational amplifier is set as differential with an external resistor network.
8.2.2.1 Differential Amplifier Equations
Equation 1 and Equation 2 are used to calculate VOUT.
1
1
2 g
g g 2 1 2
OUT 1 2
1 1
2 2
R
1 R
R
R12 R R
R R R V V
V (V V )
R R
R 2
1 1
R R
æ ö
æ ö
ç ÷
+ +
ç ÷
-ç ÷
ç ÷
+è ø
= ´ + -
ç ÷
ç ÷
+ +
ç ÷
ç ÷
è ø
(1)
1
1
2 g
g g 2
OUT BAT S Load
1 1
2 2
R
1 R
R
R12 R R
R R R
V V R I
R R
R1 1
R R
æ ö
æ ö
ç ÷
+ +
ç ÷
-ç ÷
ç ÷
è ø
= ´ + ´ ´
ç ÷
ç ÷
+ +
ç ÷
ç ÷
è ø
(2)
In an ideal case, Equation 3 then calculates R1 = R and R2 = Rg, and VOUT:
g
OUT S Load
R
V R I
R
= ´ ´
(3)
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I TEXAS INSTRUMENTS T i R v0 7 v R 0 E
However, the resistors have tolerances; therefore, the resistors cannot be perfectly matched.
R1 = R ± ΔR1
R2 = R2 ± ΔR2
R = R ± ΔR
Rg = Rg ± ΔRg
DR
Tol
R
=
(4)
Equation 5 shows that by developing the equations and neglecting the second order, the worst case is when the
tolerances add up:
g g
OUT BAT S LOAD
g g
R R
2R
V (4 Tol) V 1 2 Tol 1 R I
R R R R R
æ ö
æ ö
ç ÷
= ± ´ + ± ç + ÷ ´ ´
ç ÷
ç ÷
+ +
è ø
è ø
(5)
where
• Tol = 0.01 for 1%
• Tol = 0.001 for 0.1%
If the resistors are perfectly matched, then Tol = 0 and Equation 6 calculates VOUT:
g
OUT S LOAD
R
V R I
R
= ´ ´
(6)
The highest error is from the common mode:
g
BAT
g
R
4 (Tol) V
R R
´
+
(7)
Gain of 10, Rg / R = 10, and Tol = 1%:
Common mode error = ((4 × 0.01) / 1.1) × 12 V = 0.436 V
Gain of 10 and Tol = 0.1%:
Common mode error = 43.6 mV
The resistors were chosen from 2% batches.
R1 and R 12 kΩ
R2 and Rg 120 kΩ
Ideal Gain = 120 / 12 = 10
The measured value of the resistors:
R1 = 11.835 kΩ
R = 11.85 kΩ
R2 = 117.92 kΩ
Rg = 118.07 kΩ
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w TEXAS INSTRUMENTS ‘2 12
8.2.3 Application Curves
Load Current (A)
Output Voltage (V)
0 0.2 0.4 0.6 0.8 1 1.2
0
0.2
0.4
0.6
0.8
1
1.2
D001
Measured
Ideal
Figure 8-3. Output Voltage Measured vs Ideal
(0 A to 1 A)
Load Current (A)
Output Voltage (V)
0 2 4 6 8 10 12
0
2
4
6
8
10
12
D001
Measured
Ideal
Figure 8-4. Output Voltage Measured vs Ideal
(0 A to 10 A)
8.3 Power Supply Recommendations
Supply voltage is 4.4 V to 16 V for single supply and ±2.2 V to ±8 V for dual. In the high-side sensing application,
the supply is connected to a 12-V battery.
8.4 Layout
8.4.1 Layout Guidelines
The TLC227x-Q1 is a wideband amplifier. To realize the full operational performance of the device, good high
frequency printed-circuit-board (PCB) layout practices are required. Low-loss 0.1-μF bypass capacitors must be
connected between each supply pin and ground as close to the device as possible. The bypass capacitor traces
must be designed for minimum inductance.
8.4.2 Layout Example
+
–
RIN
RG
VIN
RF
VOUT
Figure 8-5. Schematic Representation
VOUT
NC
–IN
+IN
V–
NC
V+
OUT
NC
VS+
GND
RG
RIN
VS–
(or GND for single supply)
GND
GND
Only needed for
dual-supply
operation
VIN
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors RF
Use low-ESR ceramic
bypass capacitor
Ground (GND) plane on another layer
Figure 8-6. Operational Amplifier Board Layout for Noninverting Configuration
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I TEXAS INSTRUMENTS
9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• G.R. Boyle, D.O. Pederson, B.M. Cohn, J.E. Solomon (Dec. 1974). Macromodeling of Integrated Circuit
Operational Amplifiers. IEEE Journal of Solid-State Circuits, Volume 9, Issue 6, pages 353–364. Retrieved
from https://ieeexplore.ieee.org/document/1050528
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
LinCMOS™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
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l TEXAS INSTRUMENTS Am
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC2272AQDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272AQ
TLC2272AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272AQ
TLC2272AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272AQ
TLC2272AQPWRQ1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272AQ
TLC2272QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272Q1
TLC2272QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272Q1
TLC2272QPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272Q1
TLC2272QPWRQ1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2272Q1
TLC2274AQDRG4Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274AQ1
TLC2274AQDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274AQ1
TLC2274AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274AQ1
TLC2274AQPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274AQ1
TLC2274QDRG4Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274Q1
TLC2274QDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274Q1
TLC2274QPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274Q1
TLC2274QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2274Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2021
Addendum-Page 2
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1 :
•Catalog : TLC2272, TLC2272A, TLC2274, TLC2274A
•Enhanced Product : TLC2272A-EP, TLC2274-EP, TLC2274A-EP
•Military : TLC2272M, TLC2272AM, TLC2274M, TLC2274AM
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2021
Addendum-Page 3
•Military - QML certified for Military and Defense Applications
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC2272AQPWRG4Q1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC2272AQPWRQ1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC2272QPWRG4Q1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC2272QPWRQ1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC2274AQPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC2274AQPWRQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC2274QPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC2274QPWRQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2272AQPWRG4Q1 TSSOP PW 8 2000 356.0 356.0 35.0
TLC2272AQPWRQ1 TSSOP PW 8 2000 356.0 356.0 35.0
TLC2272QPWRG4Q1 TSSOP PW 8 2000 356.0 356.0 35.0
TLC2272QPWRQ1 TSSOP PW 8 2000 356.0 356.0 35.0
TLC2274AQPWRG4Q1 TSSOP PW 14 2000 356.0 356.0 35.0
TLC2274AQPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0
TLC2274QPWRG4Q1 TSSOP PW 14 2000 356.0 356.0 35.0
TLC2274QPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0
Pack Materials-Page 2
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
PW0008A '
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
PW0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PW0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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