ISOW784x Datasheet by Texas Instruments

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ISOW784x High-Performance, 5000-VRMS Reinforced Quad-Channel Digital Isolators

with Integrated High-Efficiency, Low-Emissions DC-DC Converter

1 Features

• 100 Mbps data rate

• Robust isolation barrier:

– >100-Year projected lifetime at 1 kVRMS

working voltage

– Up to 5000 VRMS isolation rating

– Up to 10 kVPK surge capability

– ±100 kV/µs minimum CMTI

• Integrated high-efficiency DC-DC converter with

on-chip transformer

• 3-V to 5.5-V Wide input supply range

• Regulated 5-V or 3.3-V output

• Up to 0.65-W output power

• 5 V to 5 V; 5 V to 3.3 V: Available load current ≥

130 mA

• 3.3 V to 3.3 V: Available load current ≥ 75 mA

• 3.3 V to 5 V: Available load current ≥ 40 mA

• Soft-start to limit inrush current

• Overload and short-circuit protection

• Thermal shutdown

• Default output: High and Low options

• Low propagation delay: 13 ns Typ (5-V supply)

• Robust electromagnetic compatibility (EMC)

– System-level ESD, EFT, and surge immunity

– ±8 kV IEC 61000-4-2 contact discharge

protection across isolation barrier

– Low emissions

• 16-pin Wide SOIC package

• Extended temperature range: –40°C to +125°C

• Safety-related certifications:

– 7071-VPK reinforced isolation per DIN V VDE V

0884-11:2017-01

– 5000-VRMS isolation for 1 minute per UL 1577

– CSA Certification per IEC 60950-1, IEC

62368-1 and IEC 60601-1 end equipment

standards

– CQC Approval per GB4943.1-2011

– TUV Certification according to EN 60950-1 and

EN 61010-1

2 Applications

•Industrial automation

•Motor control

•Grid infrastructure

•Medical equipment

•Test and measurement

3 Description

The ISOW784x is a family of high-performance, quad-

channel reinforced digital isolators with an integrated

high-efficiency power converter. The integrated DC-

DC converter provides up to 650 mW of isolated

power at high efficiency and can be configured

for various input and output voltage configurations.

Therefore these devices eliminate the need for a

separate isolated power supply in space-constrained

isolated designs.

Device Information

PART NUMBER(1) PACKAGE BODY SIZE (NOM)

ISOW7840

ISOW7841

ISOW7842

ISOW7843

ISOW7844

SOIC (16) 10.30 mm × 7.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DC-DC

Primary

DC-DC

Secondary

VCC VISO

OUTx

VSO

Isolation Capacitors

Isolation Transformer

GNDI GNDO

VSI

INx

VCC is the primary supply voltage referenced to GND1. VISO is

the isolated supply voltage referenced to GND2.

VSI and VSO can be either VCC or VISO depending on the

channel direction.

VSI is the input-side supply voltage referenced to GNDI and

VSO is the output-side supply voltage referenced to GNDO.

Simplified Schematic

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 5

6 Pin Configuration and Functions...................................5

Pin Functions.................................................................... 7

7 Specifications.................................................................. 9

7.1 Absolute Maximum Ratings........................................ 9

7.2 ESD Ratings............................................................... 9

7.3 Recommended Operating Conditions.........................9

7.4 Thermal Information..................................................10

7.5 Power Ratings...........................................................10

7.6 Insulation Specifications............................................11

7.7 Safety-Related Certifications.................................... 12

7.8 Safety Limiting Values...............................................12

7.9 Electrical Characteristics—5-V Input, 5-V Output..... 13

7.10 Supply Current Characteristics—5-V Input, 5-V

Output..........................................................................14

7.11 Electrical Characteristics—3.3-V Input, 5-V

Output..........................................................................16

7.12 Supply Current Characteristics—3.3-V Input, 5-

V Output...................................................................... 17

7.13 Electrical Characteristics—5-V Input, 3.3-V

Output..........................................................................18

7.14 Supply Current Characteristics—5-V Input, 3.3-

V Output...................................................................... 19

7.15 Electrical Characteristics—3.3-V Input, 3.3-V

Output..........................................................................22

7.16 Supply Current Characteristics—3.3-V Input,

3.3-V Output................................................................ 23

7.17 Switching Characteristics—5-V Input, 5-V Output.. 26

7.18 Switching Characteristics—3.3-V Input, 5-V

Output..........................................................................26

7.19 Switching Characteristics—5-V Input, 3.3-V

Output..........................................................................26

7.20 Switching Characteristics—3.3-V Input, 3.3-V

Output..........................................................................26

7.21 Insulation Characteristics Curves........................... 27

7.22 Typical Characteristics............................................28

8 Parameter Measurement Information.......................... 33

9 Detailed Description......................................................34

9.1 Overview................................................................... 34

9.2 Functional Block Diagram......................................... 35

9.3 Feature Description...................................................36

9.4 Device Functional Modes..........................................37

10 Application and Implementation................................ 39

10.1 Application Information........................................... 39

10.2 Typical Application.................................................. 39

11 Power Supply Recommendations..............................42

12 Layout...........................................................................43

12.1 Layout Guidelines................................................... 43

12.2 Layout Example...................................................... 44

13 Device and Documentation Support..........................45

13.1 Device Support....................................................... 45

13.2 Documentation Support.......................................... 45

13.3 Related Links.......................................................... 45

13.4 Receiving Notification of Documentation Updates..45

13.5 Support Resources................................................. 45

13.6 Trademarks.............................................................45

13.7 Electrostatic Discharge Caution..............................46

13.8 Glossary..................................................................46

14 Mechanical, Packaging, and Orderable

Information.................................................................... 47

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (March 2019) to Revision G (August 2021) Page

• Added 3.3 V to 5 V power converter support throughout....................................................................................1

• Removed references to 100 uF capacitor throughout........................................................................................ 1

• Removed paragraph discussing secondary VISO monitoring.......................................................................... 42

Changes from Revision E (November 2017) to Revision F (March 2019) Page

• Made editorial and cosmetic changes throughout the document....................................................................... 1

• Added "Robust Isolation Barrier" bullet in Features ...........................................................................................1

• Added ">100-Year Projected Lifetime at 1 kVRMS Working Voltage" bullet in Features .....................................1

• Added "Up to 5000 VRMS Isolation Rating" bullet in Features ........................................................................... 1

• Added "Up to 10 kVPK Surge Capability" bullet in Features .............................................................................. 1

• Added "±8 kV IEC 61000-4-2 Contact Discharge Protection across Isolation Barrier" bullet in Features ......... 1

• Updated Simplified Schematic to show two isolation capacitors in series instead of a single capacitor for

signal isolation channels ....................................................................................................................................1

• Added "Contact discharge per IEC 61000-4-2; Isolation barrier withstand test" specification of ±8000 in

Section 7.2 table................................................................................................................................................. 9

• Added table note "IEC ESD strike is applied across the barrier with all pins on each side tied together

creating a two-terminal device" to Section 7.2 table...........................................................................................9

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• Deleted "TJ or Junction temperature" parameter from Section 7.3 table as it is already specified in Section 7.1

table.................................................................................................................................................................... 9

• Added "see Figure 10-5" to TEST CONDITIONS of VIOWM specification......................................................... 11

• Added the following note to Figure 8-2: "Optional 100 µF capacitor can be added between VCC and GND1;

refer to Section 11" .......................................................................................................................................... 33

• Added the following note to Isolated Power and SPI for ADC Sensing Application with ISOW7841-Q1:

"Optional 100 µF capacitor can be added between VCC and GND1; refer to Power Supply Recommendations"

..........................................................................................................................................................................39

• Added the following text to Section 10.2.1: "Optional 100 µF decoupling capacitor can be added between VCC

and GND1 pins; refer to Section 11 for more details........................................................................................ 39

• Added the following note to Figure 10-2: "Optional 100 µF capacitor can be added between VCC and GND1;

refer to Section 11" .......................................................................................................................................... 40

• Added Section 10.2.3.1 sub-section under Section 10.2.3 section.................................................................. 41

• Added text to Section 11 section to emphasise that input decoupling capacitor should be larger than output

capacitor by at least 100 µF .............................................................................................................................42

• Added the following note to Figure 12-1: "Optional 100 µF capacitor can be added between VCC and GND1;

refer to Section 11" .......................................................................................................................................... 44

Changes from Revision D (November 2017) to Revision E (November 2017) Page

• Changed the ISOW7843 device from Preview to Production Data ................................................................... 5

• Added the ISOW7843 current parameters to each Supply Current Characteristics table ............................... 14

• Added the supply current versus data rate graphs for the ISOW7843 in the Typical Characteristics section.. 28

Changes from Revision C (October 2017) to Revision D (November 2017) Page

• Changed the ISOW7840 device from Preview to Production Data ................................................................... 5

• Added the ISOW7840 current parameters to each Supply Current Characteristics table ............................... 14

• Changed IISO to ILOAD and the value of wave clock input from 0.5, 5, and 50 MHz to 1, 10, and 100 Mbps in

the test conditions for the ISOW7841 current parameters in each Supply Current Characteristics table ....... 14

• Deleted no external ILOAD test condition for the current available to isolated supply parameter for the

ISOW7842 and ISOW7844 devices in each Supply Current Characteristics table ......................................... 14

• Changed the labels of the curves in the Thermal Derating Curve for Safety Limiting Current per VDE ..........27

• Added the supply current versus data rate graphs for the ISOW7840 in the Typical Characteristics section.. 28

• Changed the ground symbols for the input schematic for devices with F suffix and the SEL pin in the Device

I/O Schematics figure....................................................................................................................................... 38

Changes from Revision B (June 2017) to Revision C (October 2017) Page

• Changed the Safety-Related Certifications Features list.................................................................................... 1

• Changed header row From: DIN V VDE 0884-10 (VDE V 0884-10): 2016-12 To: DIN V VDE 0884-11:2017-01

in the Insulation Specifications .........................................................................................................................11

• Changed VIOSM test conditions in Insulation Specifications .............................................................................11

• Changed VISO(UL) test conditions in Insulation Specifications ..........................................................................11

• Changed the Safety-Related Certifications table..............................................................................................12

• Changed Note 1 of the Safety Limiting Values table........................................................................................ 12

• Added the ISOW7842 current parameters to each Supply Current table ........................................................14

• Added the supply current versus data rate graphs for the ISOW7842 in the Typical Characteristics section.. 28

Changes from Revision A (March 2017) to Revision B (June 2017) Page

• Added the ISOW7844 current parameters to each Supply Current table ........................................................14

Changes from Revision * (March 2017) to Revision A (March 2017) Page

• Changed the maximum propagation delay time and the typical and maximum values for pulse width distortion

in all Switching Characteristics tables...............................................................................................................26

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• Changed the maximum limit for output signal rise and fall times from 3 to 4 ns in the Switching Characteristics

—5-V Input, 3.3-V Output table........................................................................................................................ 26

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5 Description (continued)

The ISOW784x family of devices provides high electromagnetic immunity and low emissions while isolating

CMOS or LVCMOS digital I/Os. The signal-isolation channel has a logic input and output buffer separated by

a double capacitive silicon dioxide (SiO2) insulation barrier, whereas, power isolation uses on-chip transformers

separated by thin film polymer as insulating material. Various configurations of forward and reverse channels are

available. If the input signal is lost, the default output is high for the ISOW784x devices without the F suffix and

low for the devices with the F suffix (see VSI and VSO can be either VCC or VISO depending on the channel

direction).

These devices help prevent noise currents on data buses, such as RS-485, RS-232, and CAN, or other circuits

from entering the local ground and interfering with or damaging sensitive circuitry. Through innovative chip

design and layout techniques, electromagnetic compatibility of the device has been significantly enhanced to

ease system-level ESD, EFT, surge and emissions compliance. The high-efficiency of the power converter

allows operation at a higher ambient temperature. The device is available in a 16-pin SOIC wide-body (SOIC-

WB) DWE package.

6 Pin Configuration and Functions

VCC

GND1

INA

INB

INC

IND

GND1

VISO

GND2

OUTA

OUTB

OUTC

OUTD

SEL

GND2

ISOLATION

Figure 6-1. ISOW7840 DWE Package 16-Pin SOIC-WB Top View

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VCC

GND1

INA

INB

INC

OUTD

GND1

VISO

GND2

OUTA

OUTB

OUTC

IND

SEL

GND2

ISOLATION

Figure 6-2. ISOW7841 DWE Package 16-Pin SOIC-WB Top View

VCC

GND1

INA

INB

OUTC

OUTD

GND1

VISO

GND2

OUTA

OUTB

INC

IND

SEL

GND2

ISOLATION

Figure 6-3. ISOW7842 DWE Package 16-Pin SOIC-WB Top View

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VCC

GND1

INA

OUTB

OUTC

OUTD

GND1

VISO

GND2

OUTA

INB

INC

IND

SEL

GND2

ISOLATION

Figure 6-4. ISOW7843 DWE Package 16-Pin SOIC-WB Top View

VCC

GND1

OUTA

OUTB

OUTC

OUTD

GND1

VISO

GND2

INA

INB

INC

IND

SEL

GND2

ISOLATION

Figure 6-5. ISOW7844 DWE Package 16-Pin SOIC-WB Top View

Pin Functions

I/O DESCRIPTION

NAME NO.

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844

GND1 2, 8 2, 8 2, 8 2, 8 2, 8 — Ground connection for VCC

GND2 9, 15 9, 15 9, 15 9, 15 9, 15 — Ground connection for VISO

INA 3 3 3 3 14 I Input channel A

INB 4 4 4 13 13 I Input channel B

INC 5 5 12 12 12 I Input channel C

IND 6 11 11 11 11 I Input channel D

NC 7 7 7 7 7 — Not connected

OUTA 14 14 14 14 3 O Output channel A

OUTB 13 13 13 4 4 O Output channel B

OUTC 12 12 5 5 5 O Output channel C

OUTD 11 6 6 6 6 O Output channel D

SEL 10 10 10 10 10 I

VISO selection pin. VISO = 5 V when SEL shorted to VISO.

VISO = 3.3 V, when SEL shorted to GND2 or when left

floating. For more information see the Section 9.4.

VCC 1 1 1 1 1 — Supply voltage

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I/O DESCRIPTION

NAME NO.

ISOW7840 ISOW7841 ISOW7842 ISOW7843 ISOW7844

VISO 16 16 16 16 16 — Isolated supply voltage determined by SEL pin

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7 Specifications

7.1 Absolute Maximum Ratings

See (1) (2)

MIN MAX UNIT

VCC Supply voltage –0.5 6 V

VISO Isolated supply voltage –0.5 6 V

VIO Voltage at INx, OUTx, SEL pins –0.5 VCC + 0.5,

VISO + 0.5(3) V

IOMaximum output current through data channels –15 15 mA

TJJunction temperature 150 °C

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage

values.

(3) This value depends on whether the pin is located on the VCC or VISO side. The maximum voltage at the I/O pins should not exceed 6 V.

7.2 ESD Ratings

VALUE UNIT

V(ESD)

Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3) ±8000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.

7.3 Recommended Operating Conditions

(1)

MIN NOM MAX UNIT

VCC Supply voltage 3 5.5 V

IOH High level output current(2) VSO (1) = 5 V –4 mA

VSO = 3.3 V –2

IOL Low level output current(2) VSO = 5 V 4 mA

VSO = 3.3 V 2

VIH High-level input voltage 0.7 × VSI VSI V

VIL Low-level input voltage 0 0.3 × VSI V

DR Data rate 100 Mbps

TAAmbient temperature –40 125 °C

(1) VSI is the input side supply, VSO is the output side supply

(2) This current is for data output channel.

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TEXAS INSTRUMENTS cc hso TJ TA L

7.4 Thermal Information

THERMAL METRIC(1)

ISOW784x

UNITDWE (SOIC)

16 PINS

RθJA Junction-to-ambient thermal resistance 56.8 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 15.6 °C/W

RθJB Junction-to-board thermal resistance 28.5 °C/W

ΨJT Junction-to-top characterization parameter 2.4 °C/W

ΨJB Junction-to-board characterization parameter 28.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

VCC = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PDMaximum power dissipation (both sides) 1.02 W

PD1 Maximum power dissipation (side-1) 0.51 W

PD2 Maximum power dissipation (side-2) 0.51 W

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7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT

GENERAL

CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm

CPG External creepage(1) Shortest terminal-to-terminal distance across the

package surface >8 mm

DTI Distance through the insulation

Minimum internal gap (internal clearance – capacitive

signal isolation) > 21

µm

Minimum internal gap (internal clearance –

transformer power isolation) >120

CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V

Material group According to IEC 60664-1 I

Overvoltage category per IEC 60664-1

Rated mains voltage ≤ 300 VRMS I-IV

Rated mains voltage ≤ 600 VRMS I-IV

Rated mains voltage ≤ 1000 VRMS I-III

DIN V VDE 0884-11:2017-01(2)

VIORM

Maximum repetitive peak isolation

voltage AC voltage (bipolar) 1414 VPK

VIOWM Maximum working isolation voltage

AC voltage; Time dependent dielectric breakdown

(TDDB) Test; See Figure 10-5 1000 VRMS

DC voltage 1414 VDC

VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60 s (qualification);

VTEST = 1.2 × VIOTM; t = 1 s (100% production) 7071 VPK

VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform,

VTEST = 1.6 × VIOSM = 10000 VPK(qualification) 6250 VPK

qpd Apparent charge(4)

Method a, after input/output safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.2 × VIORM, tm = 10 s

≤ 5

Method a, after environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s ≤ 5

Method b1, at routine test (100% production) and

preconditioning (type test),

Vini = 1.2 × VIOTM, tini = 1 s;

Vpd(m) = 1.875 × VIORM, tm = 1 s

≤ 5

CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~3.5 pF

RIO Insulation resistance(5)

VIO = 500 V, TA = 25°C > 1012

ΩVIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011

VIO = 500 V, TS = 150°C > 109

Pollution degree 2

Climatic category 40/125/21

UL 1577

VISO(UL) Withstand isolation voltage

VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),

VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%

production)

5000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal

in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

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7.7 Safety-Related Certifications

VDE CSA UL CQC TUV

Certified according to DIN

V VDE V 0884-11:2017-01

Certified according to IEC

60950-1, IEC 62368-1, and IEC

60601-1

Recognized under

UL 1577 Component

Recognition Program

Certified according to

GB 4943.1-2011

Certified according to EN

61010-1:2010 and EN

60950- 1:2006/A2:2013

Reinforced insulation;

Maximum transient

isolation voltage, 7071

VPK;

Maximum repetitive peak

isolation voltage, 1414

VPK;

Maximum surge isolation

voltage, 6250 VPK

Reinforced insulation per

CSA 60950-1-07+A1+A2, IEC

60950-1 2nd Ed.+A1+A2, CSA

62368-1-14 and IEC 62368-1

2nd Ed., 800 VRMS maximum

working voltage (pollution

degree 2, material group I);

2 MOPP (Means of Patient

Protection) per CSA 60601-1:14

and IEC 60601-1 Ed. 3+A1, 250

VRMS maximum working voltage;

Temperature rating is 90°C

for reinforced insulation and

125°C for basic insulation; see

certificate for details.

Single protection, 5000

VRMS

Reinforced Insulation,

Altitude ≤ 5000 m,

Tropical Climate, 700

VRMS maximum working

voltage;

5000 VRMS Reinforced

insulation per EN 61010-

1:2010 up to working

voltage of 600 VRMS;

5000 VRMS Reinforced

insulation per EN 60950-

1:2006/A2:2013 up to

working voltage of 800

VRMS

Certificate number:

40040142

Master contract number: 220991 File number: E181974 Certificate number:

CQC15001121716

Client ID number: 77311

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISSafety input, output, or supply current(1)

RθJA = 56.8°C/W, VI = 5.5 V, TJ = 150°C,

TA = 25°C, see Figure 7-1 400

RθJA = 56.8°C/W, VI = 3.6 V, TJ = 150°C,

TA = 25°C, see Figure 7-1 611

PSSafety input, output, or total power(1) RθJA = 56.8°C/W, TJ = 150°C, TA = 25°C,

see Figure 7-2 2200 mW

TSMaximum safety temperature(1) 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The

IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be

exceeded. These limits vary with the ambient temperature, TA.

The junction-to-air thermal resistance, RθJA, in the Section 7.4 table is that of a device installed on a high-K test board for leaded

surface-mount packages. Use the following equations to calculate the value for each parameter:

TJ = TA + RθJA × P, where P is the power dissipated in the device.

TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.

PS = IS × VI, where VI is the maximum input voltage.

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7.9 Electrical Characteristics—5-V Input, 5-V Output

VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VISO Isolated supply voltage External IISO = 0 to 50 mA 4.75 5.07 5.43 V

External IISO = 0 to 130 mA 4.5 5.07 5.43

VISO(LINE) DC line regulation IISO = 50 mA, VCC = 4.5 V to 5.5 V 2 mV/V

VISO(LOAD) DC load regulation IISO = 0 to 130 mA 1%

EFF Efficiency at maximum load

current

IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;

VI = VSI (ISOW784x); VI = 0 V (ISOW784x

with F suffix)

53%

VCC+(UVLO)

Positive-going UVLO threshold

on VCC, VISO

2.7 V

VCC–(UVLO)

Negative-going UVLO threshold

on VCC, VISO

2.1 V

VHYS (UVLO)

UVLO threshold hysteresis on

VCC, VISO

0.2 V

VITH Input pin rising threshold 0.7 VSI

VITL Input pin falling threshold 0.3 VSI

VI(HYS)

Input pin threshold hysteresis

(INx) 0.1 VSI

IIL Low level input current VIL = 0 at INx or SEL –10 µA

IIH High level input current VIH = VSI (1) at INx or SEL 10 µA

VOH High level output voltage IO = –4 mA, see Figure 8-1 VSO (1) –

0.4 VSO – 0.2 V

VOL Low level output voltage IO = 4 mA, see Figure 8-1 0.2 0.4 V

CMTI Common mode transient

immunity VI = VSI or 0 V, VCM = 1000 V; see Figure 8-2 100 kV/us

ICC_SC

DC current from supply under

short circuit on VISO

VISO shorted to GND2 137 mA

VISO(RIP)

Output ripple on isolated supply

(pk-pk)

20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,

IISO = 130 mA 100 mV

(1) VSI = input side supply; VSO = output side supply

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7.10 Supply Current Characteristics—5-V Input, 5-V Output

VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7840

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7840);

VI = VSI (1) (ISOW7840 with F suffix) 23

No external ILOAD; VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 17

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7840);

VI = VSI (ISOW7840 with F suffix) 128

VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 111

ISOW7841

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7841);

VI = VSI (1) (ISOW7841 with F suffix) 23

No external ILOAD; VI = VSI (ISOW7841);

VI = 0 V (ISOW7841 with F suffix) 17

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7841); VI = VSI (ISOW7841 with F suffix) 128

VI = VSI (ISOW7841); VI = 0V (ISOW7841 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 112

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VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7842

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7842);

VI = VSI (1) (ISOW7842 with F suffix) 24

No external ILOAD; VI = VSI (ISOW7842);

VI = 0 V (ISOW7842 with F suffix) 18

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7842);

VI = VSI (ISOW7842 with F suffix) 126

VI = VSI (ISOW7842);

VI = 0 V (ISOW7842 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 116

ISOW7843

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7843);

VI = VSI (1) (ISOW7843 with F suffix) 25

No external ILOAD; VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 17

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7843);

VI = VSI (ISOW7843 with F suffix) 125

VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 126

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 120

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VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7844

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7844);

VI = VSI (1) (ISOW7844 with F suffix) 26

No external ILOAD; VI = VSI (ISOW7844);

VI = 0 V (ISOW7844 with F suffix) 17

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7844);

VI = VSI (ISOW7844 with F suffix) 123

VI = VSI (ISOW7844);

VI = 0 V (ISOW7844 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 126

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 126

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 126

(1) VSI = input side supply; VSO = output side supply

(2) Current available to load should be derated by 2 mA/°C for TA > 80°C.

7.11 Electrical Characteristics—3.3-V Input, 5-V Output

VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VISO Isolated supply voltage External IISO = 0 to 40 mA 4.5 5.07 5.43 V

VISO(LINE) DC line regulation IISO = 20 mA, VCC = 4.5 V to 5.5 V 2 mV/V

VISO(LOAD) DC load regulation IISO = 0 to 40 mA 1%

EFF Efficiency at maximum load

current

IISO = 40 mA, CLOAD = 0.1 µF || 10 µF;

VI = VSI (ISOW7841A-Q1); VI =0 V

(ISOW7841A-Q1 with F suffix)

42%

VCC+(UVLO)

Positive-going UVLO threshold

on VCC, VISO

2.7 V

VCC–(UVLO)

Negative-going UVLO threshold

on VCC, VISO

2.1 V

VHYS (UVLO)

UVLO threshold hysteresis on

VCC, VISO

0.2 V

VITH Input pin rising threshold 0.7 VSI

VITL Input pin falling threshold 0.3 VSI

VI(HYS)

Input pin threshold hysteresis

(INx) 0.1 VSI

IIL Low level input current VIL = 0 at INx or SEL –10 µA

IIH High level input current VIH = VSI (1) at INx or SEL 10 µA

VOH High level output voltage IO = –4 mA, see Figure 8-1 VSO (1) –

0.4 VSO – 0.2 V

VOL Low level output voltage IO = 4 mA, seeFigure 8-1 0.2 0.4 V

CMTI Common mode transient

immunity VI = VSI or 0 V, VCM = 1000 V; see Figure 8-2 100 kV/us

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I TEXAS INSTRUMENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ICC_SC

DC current from supply under

short circuit on VISO

VISO shorted to GND2 137 mA

VISO(RIP)

Output ripple on isolated supply

(pk-pk)

20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,

IISO = 40 mA 90 mV

(1) VSI = input side supply; VSO = output side supply

7.12 Supply Current Characteristics—3.3-V Input, 5-V Output

VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7841

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7841);

VI = VSI (1) (ISOW7841 with F suffix) 31

No external ILOAD; VI = VSI (ISOW7841);

VI = 0V (ISOW7841 with F suffix) 24

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) ((2))Current available to

isolated supply

VI = 0 V (ISOW7841); VI = VSI (ISOW7841 with F suffix) 38

VI = VSI (ISOW7841); VI = 0V (ISOW7841 with F suffix) 40

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 38

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 37

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 22

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TEXAS INSTRUMENTS cc

7.13 Electrical Characteristics—5-V Input, 3.3-V Output

VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VISO Isolated supply voltage External IISO = 0 to 50 mA 3.13 3.34 3.56 V

External IISO = 0 to 130 mA 3 3.34 3.56

VISO(LINE) DC line regulation IISO = 50 mA, VCC = 4.5 V to 5.5 V 2 mV/V

VISO(LOAD) DC load regulation IISO = 10 to 130 mA 1%

EFF Efficiency at maximum load

current

IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;

VI = VSI (ISOW784x); VI = 0 V (ISOW784x

with F suffix)

48%

VCC+(UVLO)

Positive-going UVLO threshold

on VCC, VISO

2.7 V

VCC–(UVLO)

Negative-going UVLO threshold

on VCC, VISO

2.1 V

VHYS (UVLO)

UVLO threshold hysteresis on

VCC, VISO

0.2 V

VITH Input pin rising threshold 0.7 VSI

VITL Input pin falling threshold 0.3 VSI

VI(HYS)

Input pin threshold hysteresis

(INx) 0.1 VSI

IIL Low level input current VIL = 0 at INx or SEL –10 µA

IIH High level input current VIH = VSI (1) at INx or SEL 10 µA

VOH High level output voltage IO = –2 mA, see Figure 8-1 VSO (1) –

0.3 VSO – 0.1 V

VOL Low level output voltage IO = 2 mA, see Figure 8-1 0.1 0.3 V

CMTI Common mode transient

immunity

VI = VSI or 0 V, VCM = 1000 V; see Figure

8-2 100 kV/us

ICC_SC

DC current from supply under

short circuit on VISO

VISO shorted to GND2 137 mA

VISO(RIP)

Output ripple on isolated supply

(pk-pk)

20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,

IISO = 130 mA 100 mV

(1) VSI = input side supply; VSO = output side supply

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l TEXAS INSTRUMENTS cc

7.14 Supply Current Characteristics—5-V Input, 3.3-V Output

VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7840

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7840);

VI = VSI (1) (ISOW7840 with F suffix) 20

No external ILOAD; VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 15

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7840);

VI = VSI (ISOW7840 with F suffix) 128

VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 129

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 116

ISOW7841

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7841);

VI = VSI (1) (ISOW7841 with F suffix) 20

No external ILOAD; VI = VSI (ISOW7841);

VI = 0 V (ISOW7841 with F suffix) 14

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7841); VI = VSI (ISOW7841 with F suffix) 128

VI = VSI (ISOW7841); VI = 0 V (ISOW7841 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL= 15 pF 129

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 118

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l TEXAS INSTRUMENTS cc

VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7842

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7842);

VI = VSI (1) (ISOW7842 with F suffix) 20

No external ILOAD; VI = VSI (ISOW7842);

VI = 0 V (ISOW7842 with F suffix) 15

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7842); VI = VSI (ISOW7842 with F suffix) 126

VI = VSI (ISOW7842); VI = 0V (ISOW7842 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 128

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 119

ISOW7843

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7843);

VI = VSI (1) (ISOW7843 with F suffix) 20

No external ILOAD; VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 14

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7843);

VI = VSI (ISOW7843 with F suffix) 125

VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 127

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 123

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l TEXAS INSTRUMENTS cc

VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7844

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7844);

VI = VSI (1) (ISOW7844 with F suffix) 21

No external ILOAD; VI = VSI (ISOW7844);

VI = 0 V (ISOW7844 with F suffix) 15

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7844); VI = VSI (ISOW7844 with F suffix) 123

VI = VSI (ISOW7844); VI = 0 V (ISOW7844 with F suffix) 130

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 126

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 126

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 126

(1) VSI = input side supply; VSO = output side supply

(2) Current available to load should be derated by 2 mA/°C for TA > 105°C.

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TEXAS INSTRUMENTS cc

7.15 Electrical Characteristics—3.3-V Input, 3.3-V Output

VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VISO Isolated supply voltage External IISO = 0 to 30 mA 3.13 3.34 3.58 V

External IISO = 0 to 75 mA 3 3.34 3.58

VISO(LINE) DC line regulation IISO = 30 mA, VCC = 3 V to 3.6 V 2 mV/V

VISO(LOAD) DC load regulation IISO = 0 to 75 mA 1%

EFF Efficiency at maximum load

current

IISO = 75 mA, CLOAD = 0.1 µF || 10 µF;

VI = VSI (ISOW784x); VI = 0 V (ISOW784x with

F suffix)

47%

VCC+(UVLO)

Positive-going UVLO threshold

on VCC, VISO

2.7 V

VCC–(UVLO)

Negative-going UVLO threshold

on VCC, VISO

2.1 V

VHYS (UVLO)

UVLO threshold hysteresis on

VCC, VISO

0.2 V

VITH Input pin rising threshold 0.7 VSI

VITL Input pin falling threshold 0.3 VSI

VI(HYS)

Input pin threshold hysteresis

(INx) 0.1 VSI

IIL Low level input current VIL = 0 at INx or SEL –10 µA

IIH High level input current VIH = VSI (1) at INx or SEL 10 µA

VOH High level output voltage IO = –2 mA, see Figure 8-1 VSO (1) –

0.3

VSO –

0.1 V

VOL Low level output voltage IO = 2 mA, see Figure 8-1 0.1 0.3 V

CMTI Common mode transient

immunity VI = VSI or 0 V, VCM = 1000 V; see Figure 8-2 100 kV/us

ICC_SC

DC current from supply under

short circuit on VISO

VISO shorted to GND2 143 mA

VISO(RIP)

Output ripple on isolated supply

(pk-pk)

20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF, IISO

= 75 mA 90 mV

(1) VSI= input side supply; VSO = output side supply

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l TEXAS INSTRUMENTS cc

7.16 Supply Current Characteristics—3.3-V Input, 3.3-V Output

VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7840

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7840);

VI = VSI (1) (ISOW7840 with F suffix) 26

No external ILOAD; VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 20

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7840);

VI = VSI (ISOW7840 with F suffix) 73

VI = VSI (ISOW7840);

VI = 0 V (ISOW7840 with F suffix) 75

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 74

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 73

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 61

ISOW7841

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7841);

VI = VSI (1) (ISOW7841 with F suffix) 26

No external ILOAD; VI = VSI (ISOW7841);

VI = 0 V (ISOW7841 with F suffix) 20

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7841);

VI = VSI (ISOW7841 with F suffix) 73

VI = VSI(ISOW7841);

VI = 0 V (ISOW7841 with F suffix) 75

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 74

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 73

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 61

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l TEXAS INSTRUMENTS cc

VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7842

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7842);

VI = VSI (1) (ISOW7842 with F suffix) 28

No external ILOAD; VI = VSI (ISOW7842);

VI = 0 V (ISOW7842 with F suffix) 20

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7842);

VI = VSI (ISOW7842 with F suffix) 71

VI = VSI (ISOW7842);

VI= 0 V (ISOW7842 with F suffix) 75

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 73

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 72

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 64

ISOW7843

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7843);

VI = VSI (1) (ISOW7843 with F suffix) 28

No external ILOAD; VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 19

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7843);

VI = VSI (ISOW7843 with F suffix) 70

VI = VSI (ISOW7843);

VI = 0 V (ISOW7843 with F suffix) 75

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 72

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 72

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 68

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VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOW7844

ICC

Current drawn from

supply

No external ILOAD; VI = 0 V (ISOW7844);

VI = VSI (1) (ISOW7844 with F suffix) 30

No external ILOAD; VI = VSI (ISOW7844);

VI = 0 V (ISOW7844 with F suffix) 19

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF, No external ILOAD

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF, No external ILOAD

IISO(OUT) (2) Current available to

isolated supply

VI = 0 V (ISOW7844);

VI = VSI (ISOW7844 with F suffix) 68

VI = VSI (ISOW7844);

VI = 0 V (ISOW7844 with F suffix) 75

All channels switching with square wave clock input of 1 Mbps;

CL = 15 pF 71

All channels switching with square wave clock input of 10 Mbps;

CL = 15 pF 71

All channels switching with square wave clock input of 100 Mbps;

CL = 15 pF 71

(1) VSI = input side supply; VSO = output side supply

(2) Current available to load should be derated by 2 mA/°C for TA > 115°C.

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7.17 Switching Characteristics—5-V Input, 5-V Output

VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH, tPHL Propagation delay time See Figure 8-1 13 17.6 ns

PWD Pulse width distortion(1) |tPHL – tPLH| 0.6 4.7 ns

tSK(o) Channel-channel output skew time(2) Same-direction channels 2.5 ns

tSK(p-p) Part-part skew time(3) 4.5 ns

tr, tfOutput signal rise and fall times 2 4 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

7.18 Switching Characteristics—3.3-V Input, 5-V Output

VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH, tPHL Propagation delay time See Figure 8-1 13.5 19.6 ns

PWD Pulse width distortion(1) |tPHL – tPLH| 0.6 4.7 ns

tSK(o) Channel-channel output skew time(2) Same-direction channels 2.5 ns

tSK(p-p) Part-part skew time(3) 4.5 ns

tr, tfOutput signal rise and fall times 2 4 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

7.19 Switching Characteristics—5-V Input, 3.3-V Output

VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH, tPHL Propagation delay time See Figure 8-1 14 19.7 ns

PWD Pulse width distortion(1) |tPHL – tPLH| 0.6 4.4 ns

tSK(o) Channel-channel output skew time(2) Same-direction channels 2 ns

tSK(p-p) Part-part skew time(3) 4.5 ns

tr, tfOutput signal rise and fall times 1 4 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

7.20 Switching Characteristics—3.3-V Input, 3.3-V Output

VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH, tPHL Propagation delay time See Figure 8-1 14.5 20.2 ns

PWD Pulse width distortion(1) |tPHL – tPLH| 0.6 4.4 ns

tSK(o) Channel-channel output skew time(2) Same-direction channels 2.2 ns

tSK(p-p) Part-part skew time(3) 4.5 ns

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TEXAS INSTRUMENTS cc 700 2500

VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tr, tfOutput signal rise and fall times 1 3 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

7.21 Insulation Characteristics Curves

Ambient Temperature (qC)

Safety Limiting Current (mA)

0 20 40 60 80 100 120 140 160

100

200

300

400

500

600

700

D001

VCC = 3.6 V

VCC = 5.5 V

Figure 7-1. Thermal Derating Curve for Safety

Limiting Current per VDE

Ambient Temperature (qC)

Safety Limiting Power (mW)

0 50 100 150 200

500

1000

1500

2000

2500

D002D002

Figure 7-2. Thermal Derating Curve for Safety

Limiting Power per VDE

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7.22 Typical Characteristics

Load Current (mA)

Output Voltage (V)

0 20 40 60 80 100 120 140

3.25

3.27

3.29

3.31

3.33

3.35

3.37

3.39

3.41

3.43

3.45

VCC = 3.3 V

VCC = 5 V

VISO = 3.3 V TA = 25°C

Figure 7-3. Isolated Supply Voltage (VISO) vs Load

Current (IISO)

Load Current (mA)

Output Voltage (V)

0 20 40 60 80 100 120 140

5.05

5.1

5.15

5.2

VISO = 5 V TA = 25°C

Figure 7-4. Isolated Supply Voltage (VISO) vs Load

Current (IISO)

Load Current (mA)

Input Supply Current (mA)

0 20 40 60 80 100 120 140 160

100

125

150

175

200

225

250

275

300

VCC = 3.3 V, VISO = 3.3 V

VCC = 5 V, VISO = 3.3 V

VCC = 5 V, VISO = 5 V

VCC = 3.3 V, VISO = 5 V

TA = 25°C

Figure 7-5. ISOW7841 Supply Current (ICC) vs Load

Current (IISO)

Load Current (mA)

Efficiency (%)

0 20 40 60 80 100 120 140

100

VCC = 3.3 V, VISO = 3.3 V

VCC = 5 V, VISO = 3.3 V

VCC = 5 V, VISO = 5 V

VCC = 3.3 V, VISO = 5 V

TA = 25°C

Figure 7-6. ISOW7841 Efficiency vs Load Current

(IISO)

Load Current (mA)

Power Dissipation (mW)

0 20 40 60 80 100 120 140

160

240

320

400

480

560

640

VCC = 3.3 V, VISO = 3.3 V

VCC = 5 V, VISO = 3.3 V

VCC = 5 V, VISO = 5 V

VCC = 3.3 V, VISO = 5 V

TA = 25°C

Figure 7-7. ISOW7841 Power Dissipation vs Load

Current (IISO)

Free-Air Temperature (qC)

Isolated Output Power Supply Voltage (V)

-40 -20 0 20 40 60 80 100 120

3.2

3.25

3.3

3.35

3.4

D008

No IISO load VCC = 5 V VISO = 3.3 V

Figure 7-8. 3.3-V Isolated Supply Voltage (VISO) vs

Free-Air Temperature

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Free-Air Temperature (qC)

Isolated Output Power Supply Voltage (V)

-40 -20 0 20 40 60 80 100 120

4.94

4.99

5.04

5.09

5.14

No IISO load VCC = 5 V VISO = 5 V

Figure 7-9. 5-V Isolated Supply Voltage (VISO) vs

Free-Air Temperature

Input Supply Voltage (V)

Short-Circuit Supply Current (mA)

Short-Circuit Power (mW)

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4

90 0

95 100

100 200

105 300

110 400

115 500

120 600

125 700

130 800

Short-circuit Supply Current

Short-circuit Power

VISO shorted to GND2 TA = 25°C

Figure 7-10. Short-Circuit Supply Current (ICC) and

Power (P) vs Supply Voltage (VCC)

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D022

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = 15 pF TA = 25°C No IISO load

Figure 7-11. ISOW7840 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D023

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = no load TA = 25°C No IISO load

Figure 7-12. ISOW7840 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply current (mA)

0 25 50 75 100

100

110

120

ICC (mA) at VCC = 5 V, VISO = 5 V

ICC (mA) at VCC = 5 V, VISO = 3.3 V

ICC (mA) at VCC = 3.3 V, VISO = 3.3 V

ICC (mA) at VCC = 3.3 V, VISO = 5 V

CL = 15 pF TA = 25°C No IISO load

Figure 7-13. ISOW7841 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

ICC (mA) at VCC = 5 V, VISO = 5 V

ICC (mA) at VCC = 5 V, VISO = 3.3 V

ICC (mA) at VCC = 3.3 V, VISO = 3.3 V

ICC (mA) at VCC = 3.3 V, VISO = 5 V

CL = no load TA = 25°C No IISO load

Figure 7-14. ISOW7841 Supply Current vs Data

Rate

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Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D021

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = 15 pF TA = 25°C No IISO load

Figure 7-15. ISOW7842 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D020

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = no load TA = 25°C No IISO load

Figure 7-16. ISOW7842 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D024

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = 15 pF TA = 25°C No IISO load

Figure 7-17. ISOW7843 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D025

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = no load TA = 25°C No IISO load

Figure 7-18. ISOW7843 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D018

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = 15 pF TA = 25°C No IISO load

Figure 7-19. ISOW7844 Supply Current vs Data

Rate

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D019

ICC at VCC = 3.3 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 3.3 V

ICC at VCC = 5 V, VISO = 5 V

CL = no load TA = 25°C No IISO load

Figure 7-20. ISOW7844 Supply Current vs Data

Rate

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Free-Air Temperature (qC)

Power Supply UVLO Threshold (V)

-40 -20 0 20 40 60 80 100 120

2.1

2.2

2.3

2.4

2.5

2.6

VCC Rising

VCC Falling

Figure 7-21. Power-Supply Undervoltage

Threshold vs Free Air Temperature

Free Air Temperature (°C)

Propogation Delay Time (ns)

-40 -20 0 20 40 60 80 100 120 140

tPLH(ns) at VCC = 5 V, V ISO = 5 V

tPHL(ns) at VCC = 5 V, V ISO = 5 V

tPLH(ns) at VCC = 5 V, V ISO = 3.3 V

tPHL(ns) at VCC = 5 V, V ISO = 3.3 V

tPLH(ns) at VCC = 3.3 V, VISO = 3.3 V

tPHL(ns) at VCC = 3.3 V, VISO = 3.3 V

tPLH(ns) at VCC = 3.3 V, VISO = 5 V

tPHL(ns) at VCC = 3.3 V, VISO = 5 V

Figure 7-22. Propagation Delay Time vs Free-Air

Temperature

High-Level Output Current (mA)

High-Level Output Voltage (V)

-15 -10 -5 0

D015

VSO = 3.3 V

VSO = 5 V

TA = 25°C

Figure 7-23. High-Level Output Voltage vs High-

Level Output Current

Low-Level Output Current (mA)

Low-Level Output Voltage (V)

0 5 10 15

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

D016

VSO = 3.3 V

VSO = 5 V

TA = 25°C

Figure 7-24. Low-Level Output Voltage vs Low-

Level Output Current

VISO = 3.3 V (50 mV/div)(1)

10 mA

110 mA

10 mA

100 µs/div

IISO

VCC = 5 V VISO = 3.3 V

Negligible undershoot and overshoot because of load

transient

Figure 7-25. 10-mA to 110-mA Load Transient

Response

VISO = 3.3 V (1 V/div)

ICC (40 mA/div)

2 ms/div

VCC = 5 V VISO = 3.3 V

Current spike is because of charging the input supply

capacitor

Figure 7-26. Soft Start at 10-mA Load

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VISO = 3.3 V (1 V/div)

ICC (40 mA/div)

2 ms/div

VCC = 5 V VISO = 3.3 V

Input current spike is because of charging the input supply

decoupling capacitor

Figure 7-27. Soft Start at 120-mA Load

VISO = 5 V (1 V/div)

ICC (40 mA/div)

2 ms/div

VCC = 5 V VISO = 5 V

Input current spike is because of charging the input supply

decoupling capacitor

Figure 7-28. Soft Start at 10-mA Load

VISO = 5 V (1 V/div)

ICC (40 mA/div)

2 ms/div

VCC = 5 V VISO = 5 V

Input current spike is because of charging the input supply

decoupling capacitor

Figure 7-29. Soft Start at 130-mA Load

VISO = 5 V (20 mV/div)

5 µs/div

20 mV

VCC = 5 V VISO = 5 V

Figure 7-30. VISO Ripple Voltage at 130 mA

VISO = 3.3 V (20 mV/div)

5 µs/div

20 mV

VCC = 5 V VISO = 3.3 V

Figure 7-31. VISO Ripple Voltage at 130 mA

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8 Parameter Measurement Information

IN OUT

See Note B

VOL

VOH

VSI

0 V

Isolation Barrier

50 

Input Generator

(See Note A) VIVO

tPLH tPHL

50% 50%

90%

10%

The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO =

50 Ω. At the input, 50-Ω resistor is required to terminate the input generator signal. The resistor is not required in the actual application.

CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms

VSI

GNDI

GNDI GNDO

OUT

VSO

0.1 …F10 …F

VCM

± +

C3 C4

5 V

10 …F || 0.1 µF

CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Pass-fail criteria: Outputs must remain stable.

Figure 8-2. Common-Mode Transient Immunity Test Circuit

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9 Detailed Description

9.1 Overview

The ISOW784x family of devices has a high-efficiency, low-emissions isolated DC-DC converter, and four

high-speed isolated data channels. Figure 9-1 shows the functional block diagram of the ISOW784x family of

devices.

The integrated DC-DC converter uses switched mode operation and proprietary circuit techniques to reduce

power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of a high-Q

on-chip transformer provide high efficiency and low radiated emissions. The integrated transformer uses thin film

polymer as the insulation barrier.

The VCC supply is provided to the primary power controller that switches the power stage connected to the

integrated transformer. Power is transferred to the secondary side, rectified and regulated to either 3.3 V or 5

V, depending on the SEL pin. The output voltage, VISO, is monitored and feedback information is conveyed to

the primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted

accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots

during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VCC and VISO supplies

which ensures robust system performance under noisy conditions. An integrated soft-start mechanism ensures

controlled inrush current and avoids any overshoot on the output during power up.

The integrated signal-isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the

digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier

across the barrier to represent one state and sends no signal to represent the other state. The receiver

demodulates the signal after signal conditioning and produces the output through a buffer stage. The signal-

isolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the

radiated emissions from the high frequency carrier and IO buffer switching. Figure 9-2 shows a functional block

diagram of a typical signal isolation channel.

The ISOW784x family of devices is suitable for applications that have limited board space and require more

integration. This family of devices is also suitable for very-high voltage applications, where power transformers

meeting the required isolation specifications are bulky and expensive.

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9.2 Functional Block Diagram

Transformer

Rectifier

Transformer

Driver

Power

Controller

Thermal

Shutdown,

UVLO, Soft-start

FB Channel (Rx)

Data Channels

(4)

FB Channel (Tx)

Data Channels

(4)

VCC

FB Controller

I/O Channels

Isolation Barrier

I/O Channels

UVLO, Soft-start

Vref

VISO

Figure 9-1. Block Diagram

TX IN

Oscillator

OOK

Modulation

Transmitter

Emissions

Reduction

Techniques

TX Signal

Conditioning

Envelope

Detection

RX Signal

Conditioning

Receiver

RX OUT

SiO2 based

Capacitive

Isolation

Barrier

Figure 9-2. Conceptual Block Diagram of a Capacitive Data Channel

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Figure 9-3 shows a conceptual detail of how the OOK scheme works.

TX IN

RX OUT

Carrier signal through

isolation barrier

Figure 9-3. On-Off Keying (OOK) Based Modulation Scheme

9.3 Feature Description

Table 9-1 shows an overview of the device features.

Table 9-1. Device Features

PART NUMBER(1) CHANNEL DIRECTION MAXIMUM DATA RATE DEFAULT OUTPUT

STATE RATED ISOLATION(2)

ISOW7840 4 forward, 0 reverse

100 Mbps

High

5 kVRMS / 7071 VPK

ISOW7840F Low

ISOW7841 3 forward, 1 reverse High

ISOW7841F Low

ISOW7842 2 forward, 2 reverse High

ISOW7842F Low

ISOW7843 1 forward, 3 reverse High

ISOW7843F Low

ISOW7844 0 forward, 4 reverse High

ISOW7844F Low

(1) The F suffix is part of the orderable part number. See the Section 14 section for the full orderable part number.

(2) For detailed isolation ratings, see the Section 7.7 table.

9.3.1 Electromagnetic Compatibility (EMC) Considerations

The ISOW784x family of devices uses emissions reduction schemes for the internal oscillator and advanced

internal layout scheme to minimize radiated emissions at the system level.

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the

ISOW784x family of devices incorporates many chip-level design improvements for overall system robustness.

Some of these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

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9.3.2 Power-Up and Power-Down Behavior

The ISOW784x family of devices has built-in UVLO on the VCC and VISO supplies with positive-going and

negative-going thresholds and hysteresis. When the VCC voltage crosses the positive-going UVLO threshold

during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled

manner. This soft-start scheme limits primary peak currents drawn from the VCC supply and charges the

VISO output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an

indeterminate state until the VCC or VISO voltage crosses the positive-going UVLO threshold. When the UVLO

positive-going threshold is crossed on the secondary side VISO pin, the feedback data channel starts providing

feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the

normal state defined by the respective input channels or their default states. Design should consider a sufficient

time margin (typically 10 ms with 10-µF load capacitance) to allow this power up sequence before valid data

channels are accounted for system functionality.

When VCC power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached.

The VISO capacitor then discharges depending on the external load. The isolated data outputs on the VISO side

are returned to the default state for the brief time that the VISO voltage takes to discharge to zero.

9.3.3 Current Limit, Thermal Overload Protection

The ISOW784x family of devices is protected against output overload and short circuit. Output voltage starts

dropping when the power converter is not able to deliver the current demanded during overload conditions. For a

VISO short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.

Thermal protection is also integrated to help prevent the device from getting damaged during overload and

short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to increase.

When the temperature goes above 180°C, thermal shutdown activates and the primary controller turns off

which removes the energy supplied to the VISO load, which causes the device to cool off. When the junction

temperature goes below 150°C, the device starts to function normally. If an overload or output short-circuit

condition prevails, this protection cycle is repeated. Care should be taken in the design to prevent the device

junction temperatures from reaching such high values.

9.4 Device Functional Modes

Table 9-2 lists the supply configurations for these devices.

Table 9-2. Supply Configurations

SEL INPUT VCC VISO

Shorted to VISO 5 V 5 V

Shorted to VISO 3.3 V 5 V

Shorted to GND2 or floating 5 V 3.3 V(1)

Shorted to GND2 or floating 3.3 V 3.3 V(1)

(1) The SEL pin has a weak pulldown internally. Therefore for VISO = 3.3 V, the SEL pin should be

strongly connected to the GND2 pin in noisy system scenarios.

Table 9-3 lists the functional modes for ISOW784x devices.

Table 9-3. Function Table

INPUT SUPPLY

(VCC)(1)

INPUT

(INx)

OUTPUT

(OUTx) COMMENTS

H H Output channel assumes the logic state of its input

L L

Open Default

Default mode(2): When INx is open, the corresponding

output channel assumes logic based on default output

mode of selected version

PD X Undetermined(3)

(1) PU = Powered up (VCC ≥ 2.7 V); PD = Powered down (VCC < 2.1 V); X = Irrelevant; H = High level; L = Low level, VCC = Input-side

supply

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(2) In the default condition, the output is high for ISOW784x and low for ISOW784x with the F suffix.

(3) The outputs are in an undetermined state when VCC < 2.1 V.

9.4.1 Device I/O Schematics

Input (Devices without F suffix) Input (Devices with F suffix)

Output SEL Pin

INx

VCC VCC VCC VCC

985 

1.5 M

INx

VCC VCC VCC

985 

1.5 M

SEL

VISO VISO VISO

1970 

2 M

VISO

OUTx

~20 

Figure 9-4. Device I/O Schematics

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital

isolators require two power supplies isolated from each other to power up both sides of device. Due to the

integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used

to power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses

single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because

of the single-ended design structure, digital isolators do not conform to any specific interface standard and are

only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between

the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the

interface type or standard.

The device is suitable for applications that have limited board space and desire more integration. The device

is also suitable for very high voltage applications, where power transformers meeting the required isolation

specifications are bulky and expensive.

10.2 Typical Application

For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,

simulation results, and test results, refer to TI Design TIDA-01333, Eight-Channel, Isolated, High-Voltage

Analog Input Module With ISOW7841 Reference Design.

Figure 10-1 shows the typical schematic for SPI isolation.

MCU ISOW7841

VCC

IND

SEL

GND2

INA

INB

INC

OUTD

GND1

OUTA

OUTB

OUTC

VISO

ADC

SDO

SCLK

SDI

SCLK

SDI

SDO

AVDD DVDD

REF

AGND DGND

DVCC

DVSS

3.3VIN

3.3VOUT

Analog Input

0.1 …F22 …F22 …F0.1 …F

Reference

Figure 10-1. Isolated Power and SPI for ADC Sensing Application with ISOW7841

10.2.1 Design Requirements

To design with this device, use the parameters listed in Table 10-1.

Table 10-1. Design Parameters

PARAMETER VALUE

Input voltage 3 V to 5.5 V

Decoupling capacitor between VCC and GND1 0.1 µF to 10 µF

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Table 10-1. Design Parameters (continued)

PARAMETER VALUE

Decoupling capacitor between VISO and GND2 0.1 µF to 10 µF

Because of very-high current flowing through the ISOW7841 device VCC and VISO supplies, higher decoupling

capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is adequate, higher

decoupling capacitors (such as 47 µF) on both the VCC and VISO pins to the respective grounds are strongly

recommended to achieve the best performance.

10.2.2 Detailed Design Procedure

The devices requires only external bypass capacitors to operate. These low-ESR ceramic bypass capacitors

must be placed as close to the chip pads as possible.

INB

SEL

OUTB

VISO

GND1

VCC

GND2

INA OUTA

INC OUTC

2 mm Maximum

from Vcc

GND1

2 mm Maximum

from VISO

10 F

0.1 F

GND2

11 IND6OUTD

10 F

0.1 F

Optional 100 µF capacitor can be added between VCC and GND1; refer to Section 11.

Figure 10-2. Typical ISOW7841 Circuit Hook-Up

The VCC power-supply input provides power to isolated data channels and to the isolated DC-DC converter. Use

Equation 1 to calculate the total power budget on the primary side.

ICC = (VISO × IISO) / (η × VCC) + Iinpx (1)

where

• ICC is the total current required by the primary supply.

• VISO is the isolated supply voltage.

• IISO is the external load on the isolated supply voltage.

• η is the efficiency.

• VCC is the supply voltage.

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• Iinpx is the total current drawn for the isolated data channels and power converter when data channels are

toggling at a specific data rate. This data is shown in the Section 7.9 table.

10.2.3 Application Curve

ICC (40 mA/div)

VISO (600 mV/div)

VCC = 3.3 V IISO = 70 mA

Input current spike is because of charging the input supply decoupling capacitor

Figure 10-3. Soft-Start Waveform

10.2.3.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown

(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal

device and high voltage applied between the two sides; See Figure 10-4 for TDDB test setup. The insulation

breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced

insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million

(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation

voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for

lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%

higher than the specified value.

Figure 10-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.

Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.

DUT

Vcc 2

Vcc 1

GND 1 GND 2

Ovenat150°C

TimeCounter

> 1 mA

Figure 10-4. Test Setup for Insulation Lifetime Measurement

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1.5.12 mu m rnnsuu (< 1="" ppm="" in="" may="" tlnu="" in="" iii="" (we)="" vde="" saw="" min="" to».="" 1500="" 2m="" 2m="" mo="" we="" 4m="" 4500="" snoo="" saw="" em="" asoo="" mild="" valli!="" mid“)="" anumvm-="" «my».s="" pumalnm="" mus...-="" 1mm="" ra="" muse-c="" uphdvmm="" mummy-mm="">

Figure 10-5. Insulation Lifetime Projection Data

11 Power Supply Recommendations

To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors

must be located as close to supply pins as possible. The input supply (VCC) must have an appropriate current

rating to support output load and switching at the maximum data rate required by the end application. For more

information, refer to the Section 10.2.2 section.

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12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low-EMI PCB design (see Figure 12-1). Layer stacking

should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and

low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

• Keep decoupling capacitors as close as possible to the VCC and VISO pins.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system

to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.

Also the power and ground plane of each power system can be placed closer together, thus increasing the

high-frequency bypass capacitance significantly.

Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND

pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the

device from rising to unacceptable levels.

The integrated signal and power isolation device simplifies system design and reduces board area. The use of

low-inductance micro-transformers in the device necessitates the use of high frequency switching, resulting in

higher radiated emissions compared to discrete solutions. The device uses on-chip circuit techniques to reduce

emissions compared to competing solutions. For further reduction in radiated emissions at system level, refer to

the Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application report.

12.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength

and stiffness, and the self-extinguishing flammability-characteristics.

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12.2 Layout Example

2 mm

maximum

from VISO

Solid ground islands help

dissipate heat through PCB

Solid supply islands reduce

inductance because large peak

currents flow into the VCC pin

SEL

VISO

GND1

VCC

GND2

GND1 GND2

0.1 …F 10 …F

10 …F0.1 …F

2 mm

maximum

from VCC

Figure 12-1. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

For development support, refer to:

•8-ch Isolated High Voltage Analog Input Module with ISOW7841 Reference Design

•Isolated RS-485 With Integrated Signal and Power Reference Design

•Isolated RS-232 With Integrated Signal and Power Reference Design

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Digital Isolator Design Guide

• Texas Instruments, Isolation Glossary

• Texas Instruments, ISOW784x Quad-Channel Digital Isolator With Integrated DC-DC Converter Evaluation

Module user's guide

• Texas Instruments, Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application

report

• Texas Instruments, Overvoltage protection for isolated DC/DC convertertech note

13.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 13-1. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

ISOW7840 Click here Click here Click here Click here Click here

ISOW7841 Click here Click here Click here Click here Click here

ISOW7842 Click here Click here Click here Click here Click here

ISOW7843 Click here Click here Click here Click here Click here

ISOW7844 Click here Click here Click here Click here Click here

13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.6 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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13.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ISOW7840DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7840

ISOW7840DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7840

ISOW7840FDWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7840F

ISOW7840FDWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7840F

ISOW7841DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7841

ISOW7841DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7841

ISOW7841FDWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7841F

ISOW7841FDWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7841F

ISOW7842DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7842

ISOW7842DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7842

ISOW7842FDWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7842F

ISOW7842FDWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7842F

ISOW7843DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7843

ISOW7843DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7843

ISOW7843FDWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7843F

ISOW7843FDWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7843F

ISOW7844DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7844

ISOW7844DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7844

ISOW7844FDWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7844F

ISOW7844FDWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7844F

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn ot the carrier tape i P1 Ptlch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE a O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ISOW7840DWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7840FDWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7841DWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7841FDWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7842DWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7842FDWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7843DWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7843FDWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7844DWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISOW7844FDWER SOIC DWE 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ISOW7840DWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7840FDWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7841DWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7841FDWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7842DWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7842FDWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7843DWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7843FDWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7844DWER SOIC DWE 16 2000 350.0 350.0 43.0

ISOW7844FDWER SOIC DWE 16 2000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

ISOW7840DWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7840FDWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7841DWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7841FDWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7842DWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7842FDWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7843DWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7843FDWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7844DWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

ISOW7844FDWE DWE SO-MOD 16 40 506.98 12.7 4826 6.6

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Jan-2022

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

NOTE 4

7.6

7.4

4223098/A 07/2016

SOIC - 2.65 mm max heightDWE0016A

SOIC

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

vi““‘ 4L

www.ti.com

EXAMPLE BOARD LAYOUT

(9.75)

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

16X (1.65)

16X (0.6)

14X (1.27)

16X (2)

16X (0.6)

4223098/A 07/2016

SOIC - 2.65 mm max heightDWE0016A

SOIC

SYMM

SEE

DETAILS

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SEE

DETAILS

vm““‘+\‘\‘ maimémmﬁ A E

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.65)

16X (0.6)

14X (1.27)

(9.75)

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4223098/A 07/2016

SOIC - 2.65 mm max heightDWE0016A

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ISOW784x Datasheet by Texas Instruments

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