INA101 Datasheet by Texas Instruments

BURR - BROWN IF v w [W JFK—W TN m» M FT’Wt—t T MW ~ «W - WV‘ vW
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
FEATURES
●LOW DRIFT: 0.25µV/°C max
●LOW OFFSET VOLTAGE: 25µV max
●LOW NONLINEARITY: 0.002%
●LOW NOISE: 13nV/√Hz
●HIGH CMR: 106dB AT 60Hz
●HIGH INPUT IMPEDANCE: 1010Ω
●14-PIN PLASTIC, CERAMIC DIP,
SOL-16, AND TO-100 PACKAGES
High Accuracy
INSTRUMENTATION AMPLIFIER
APPLICATIONS
●STRAIN GAGES
●THERMOCOUPLES
●RTDs
●REMOTE TRANSDUCERS
●LOW-LEVEL SIGNALS
●MEDICAL INSTRUMENTATION
The INA101 is packaged in TO-100 metal, 14-pin
plastic and ceramic DIP, and SOL-16 surface-mount
packages. Commercial, industrial and military tem-
perature range models are available.
®
DESCRIPTION
The INA101 is a high accuracy instrumentation ampli-
fier designed for low-level signal amplification and
general purpose data acquisition. Three precision op
amps and laser-trimmed metal film resistors are inte-
grated on a single monolithic integrated circuit.
INA101
A
1
A
2
A
3
8
7
10kΩ10kΩ
10kΩ10kΩ
2
9
5
4
1
10
–Input
+Input
R
G
Offset
Adj.
+V
CC
INA101
Common
Output
20kΩ
20kΩ
3
–V
CC
6
TO-100 PACKAGE
A
1
A
2
A
3
1
14
10kΩ10kΩ
10kΩ10kΩ
6
2
12
11
4
3
–Input
+Input
R
G
Offset
Adj.
+V
CC
INA101
Common
Output
20kΩ
20kΩ
7
–V
CC
13
DIP PACKAGE
A
1
Output
8
A
2
Output
9
10
5
Gain Sense 1
Gain Set 1
Gain Set 2
Gain Sense 2
1kΩ
1kΩ
1kΩ
1kΩ
©1981 Burr-Brown Corporation PDS-454K Printed in U.S.A. July, 1998
SBOS133
sum: aRowu
®
INA101 2
SPECIFICATIONS
ELECTRICAL
At +25°C with ±15VDC power supply and in circuit of Figure 1, unless otherwise noted.
INA101AM, AG INA101SM, SG INA101CM, CG INA101HP, KU
PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
GAIN
Range of Gain 1 1000 * * * * * * V/V
Gain Equation G = 1 + (40k/RG) * * * V/V
Error from Equation, DC(1) ±(0.04 + 0.00016G ±(0.1 + 0.0003G * * * * ±(0.1 + ±(0.3 + %
–0.02/G) –0.05/G) 0.00015G) 0.0002G)
–0.05/G –0.10/G
Gain Temp. Coefficient(3)
G = 1 2 5 * * * * * * ppm/°C
G = 10 20 100 * * 10 * * * ppm/°C
G = 100 22 110 * * 11 * * * ppm/°C
G = 1000 22 110 * * 11 * * * ppm/°C
Nonlinearity, DC(2) ±(0.002 + 10–5 G) ±(0.005 + 2 x 10–5 G) ±(0.001 ±(0.002 ±(0.001 ±(0.002 * * % of p-p FS
+10–5 G) +10–5 G) +10–5 G) +10–5 G)
RATED OUTPUT
Voltage ±10 ±12.5 * * * * * * V
Current ±5±10 * * * * * * mA
Output Impedance 0.2 * * * Ω
Capacitive Load 1000 * * * pF
INPUT OFFSET VOLTAGE
Initial Offset at +25°C±(25 + 200/G) ±(50 + 400/G) ±10+ ±(25 ±(10+ ±(25 + ±(125 + ±(250 + µV
100/G) +200/G) 100/G) 200/G) 450/G) 900/G)
vs Temperature ±(2 + 20/G) ±(0.75 ±(0.25 + ±(2 + 20/G) µV/°C
+ 10/G) 10/G)
vs Supply ±(1 + 20/G) * * * µV/V
vs Time ±(1 + 20/G) * * * µV/mo
INPUT BIAS CURRENT
Initial Bias Current
(each input) ±15 ±30 ±10 * ±5±20 * * nA
vs Temperature ±0.2 * * * nA/°C
vs Supply ±0.1 * * * nA/V
Initial Offset Current ±15 ±30 ±10 * ±5±20 * * nA
vs Temperature ±0.5 * * * nA/°C
INPUT IMPEDANCE
Differential 1010 || 3 * * * Ω || pF
Common-mode 1010 || 3 * * * Ω || pF
INPUT VOLTAGE RANGE
Range, Linear Response ±10 ±12 * * * * * * V
CMR with 1kΩ Source Imbalance
DC to 60Hz, G = 1 80 90 * * * * 65 85 dB
DC to 60Hz, G = 10 96 106 * * * * 90 95 dB
DC to 60Hz, G = 100 to 1000 106 110 * * * * 100 105 dB
INPUT NOISE
Input Voltage Noise
fB = 0.01Hz to 10Hz 0.8 * * * µV, p-p
Density, G = 1000
fO = 10Hz 18 * * * nV/√Hz
fO = 100Hz 15 * * * nV/√Hz
fO = 1kHz 13 * * * nV/√Hz
Input Current Noise
fB = 0.01Hz to 10Hz 50 * * * pA, p-p
Density
fO = 10Hz 0.8 * * * pA/√Hz
fO = 100Hz 0.46 * * * pA/√Hz
fO = 1kHz 0.35 * * * pA/√Hz
DYNAMIC RESPONSE
Small Signal, ±3dB Flatness
G = 1 300 * * * kHz
G = 10 140 * * * kHz
G = 100 25 * * * kHz
G = 1000 2.5 * * * kHz
Small Signal, ±1% Flatness
G = 1 20 * * * kHz
G = 10 10 * * * kHz
G = 100 1 * * * kHz
G = 1000 200 * * * Hz
Full Power, G = 1 to 100 6.4 * * * kHz
Slew Rate, G = 1 to 100 0.2 0.4 * * * * * * V/µs
Settling Time (0.1%)
G = 1 30 40 * * * * * * µs
G = 100 40 55 * * * * * * µs
G = 1000 350 470 * * * * * * µs
Settling Time (0.01%)
G = 1 30 45 * * * * * * µs
G = 100 50 70 * * * * * * µs
G = 1000 500 650 * * * * * * µs
POWER SUPPLY
Rated Voltage ±15 * * * V
Voltage Range ±5±20 * * * * * * V
Current, Quiescent(2) ±6.7 ±8.5 * * * * * * mA
TEMPERATURE RANGE(5)
Specification –25 +85 –55 +125 * * 0 +70 °C
Operation –55 +125 * * * * –25 +85 °C
Storage –65 +150 * * * * –40 +85 °C
* Specifications same as for INA101AM, AG.
NOTES: (1) Typically the tolerance of RG will be the major source of gain error. (2) Nonlinearity is the maximum peak deviation from the best straight-line as a percentage of peak-to-peak full scale output. (3) Not including the TCR of RG. (4) Adjustable
to zero at any one gain. (5)
θ
JC output stage = 113°C/W,
θ
JC quiescent circuitry = 19°C/W,
θ
CA = 83°C/W.
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®
INA101
3
PIN CONFIGURATIONS
Top View
10
1
5
3
4
–In
+In
Gain
Set
Offset
Adjust
Offset
Adjust
Gain Set
2
9
8
7
6–V
CC
Common
Output
+V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Output
+V
CC
–Input
Gain Sense 1
Gain Set 1
Offset Adj.
Offset Adj.
Common
–V
CC
+Input
Gain Sense 2
Gain Set 2
A2 Output
A1 Output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Output
+V
CC
–Input
Gain Sense 1
Gain Set 1
Offset Adj.
Offset Adj.
NC
Common
–V
CC
+Input
Gain Sense 2
Gain Set 2
A2 Output
A1 Output
NC
DIP
G and P Package
SOIC
U Package
TO-100
M Package
ORDERING INFORMATION
PRODUCT PACKAGE TEMPERATURE RANGE
INA101AM 10-Pin Metal TO-100 –25°C to +85°C
INA101CM 10-Pin Metal TO-100 –25°C to +85°C
INA101AG 14-Pin Ceramic DIP –25°C to +85°C
INA101CG 14-Pin Ceramic DIP –25°C to +85°C
INA101HP 14-Pin Plastic DIP 0°C to +70°C
INA101KU SOL-16 Surface-Mount 0°C to +70°C
INA101SG 14-Pin Ceramic DIP –55°C to +125°C
INA101SM 10-Pin Metal TO-100 –55°C to +125°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................... ±20V
Power Dissipation .......................................................................... 600mW
Input Voltage Range .......................................................................... ±VCC
Output Short Circuit (to ground) ............................................... Continuous
Operating Temperature M, G Package ........................... –55°C to +125°C
P, U Package ................................................................. –25°C to +85°C
Storage Temperature M, G Package .............................. –65°C to +150°C
P, U Package ................................................................. –40°C to +85°C
Lead Temperature (soldering, 10s) M, G, P Package ................... +300°C
Lead Temperature (wave soldering, 3s) U Package...................... +260°C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
INA101AM 10-Pin Metal TO-100 007
INA101CM 10-Pin Metal TO-100 007
INA101AG 14-Pin Ceramic DIP 169
INA101CG 14-Pin Ceramic DIP 169
INA101HP 14-Pin Plastic DIP 010
INA101KU SOL-16 Surface-Mount 211
INA101SG 14-Pin Ceramic DIP 169
INA101SM 10-Pin Metal TO-100 007
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
\ H“
®
INA101 4
STEP RESPONSE
Time (µs)
Output (V)
0
+10
+5
0
–5
–10
100 200 300 400 500 600
G = 1000
G = 1
QUIESCENT CURRENT vs SUPPLY
Supply Voltage (V)
Quiescent Current (mA)
0
±9
±8
±7
±6
±5
±5 ±10 ±15 ±20
WARM-UP DRIFT vs TIME
Time (Minutes)
Change in Input Offset Voltage (µV)
0
10
8
6
4
2
012345
CMR vs FREQUENCY
Frequency (Hz)
CMR (dB)
1
120
100
80
60
10 100 1k 10k
G = 100, 1000
G = 10
G = 1
Balanced
Source
GAIN vs FREQUENCY
Frequency (Hz)
Gain (dB)
100
60
40
20
0
1k 10k 100k 1M
1% Error
G = 1000
G = 100
G = 10
G = 1
GAIN NONLINEARITY vs GAIN
Gain (V/V)
Gain Nonlinearity (% p-p, FS)
1 100 100010
0.01
0.003
0.001
0.0003
Max
Typ
TYPICAL PERFORMANCE CURVES
At +25°C, VCC = ±15V unless otherwise noted.
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®
INA101
5
INPUT NOISE VOLTAGE
vs FREQUENCY (100 ≤ GAIN ≤ 1000)
Frequency (Hz)
Input Noise Voltage (nV/√Hz)
0
1000
100
10
110 100 1000
OUTPUT NOISE vs GAIN
Gain (V/V)
Output Noise Voltage (mV, rms)
0
30
20
10
010 100 1000
R
S
= 1MΩ
R
S
= 1000kΩ
R
S
= 10kΩ
R
S
= 0
SETTLING TIME vs GAIN
Gain (V/V)
Settling Time (µs)
1 100 100010
1000
100
10
1%
RL = 2kΩ
CL = 1000pF 0.01%
0.1%
(1)
G = 1 +
TYPICAL PERFORMANCE CURVES (CONT)
At +25°C, VCC = ±15V unless otherwise noted.
40kΩ
RG
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA101. (Pin numbers shown are for the TO-100
metal package.) Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
The output is referred to the output Common terminal which
is normally grounded. This must be a low-impedance con-
nection to assure good common-mode rejection. A resis-
tance greater than 0.1Ω in series with the Common pin will
cause common-mode rejection to fall below 106dB.
SETTING THE GAIN
Gain of the INA101 is set by connecting a single external
resistor, RG:
The 40kΩ term in equation (1) comes from the sum of the
two internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute val-
ues. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi-
cations of the INA101.
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance which will contribute additional gain error (possi-
bly an unstable gain error) in gains of approximately 100 or
greater. The gain sense connections on the DIP and SOL-16
packages (see Figure 2) reduce the gain error produced by
wiring or socket resistance.
T T i i sunk , aRuwu
®
INA101 6
A
1
A
2
A
3
14
10kΩ10kΩ
10kΩ10kΩ
2
12
11
4
3
R
G
+15V
INA101
Common
V
O
= G (E
1
– E
2
) +V
COM
20kΩ
20kΩ
–15V
13
DIP PACKAGE
A
1
Output
A
2
Output
10
5
OPA177
1kΩ
1MΩ
+15V
–15V
Approximately
±15mV Range
Pinout shown
is for DIP packages.
E
1
E
2
G = 1 + 40kΩ
R
G
Input Offset Adjustment
Do not use to null source or system
offset (see text).
100kΩ
+15V
Output Offset
Adjustment
1
V
COM
100kΩ
67
OFFSET TRIMMING
The INA101 is laser trimmed for low offset voltage and
drift. Most applications require no external offset adjust-
ment. Figure 2 shows connection of an optional potentio-
meter connected to the Offset Adjust pins for trimming the
input offset voltage. (Pin numbers shown are for the DIP
package.) Use this adjustment to null the offset voltage in
high gain (G ≥ 100) with both inputs connected to ground.
Do not use this adjustment to null offset produced by the
source or other system offset since this will increase the
offset voltage drift by 0.3µV/°C per 100µV of adjusted
offset.
Offset of the output amplifier usually dominates when the
INA101 is used in unity gain (G = 1). The output offset
voltage can be adjusted with the optional trim circuit con-
nected to the Common pin as shown in Figure 2. The voltage
applied to Common terminal is summed with the output.
Low impedance must be maintained at this node to assure
good common-mode rejection. The op amp connected as a
buffer provides low impedance.
THERMAL EFFECTS ON OFFSET VOLTAGE
To achieve lowest offset voltage and drift, prevent air
currents from circulating near the INA101. Rapid changes in
temperature will produce a thermocouple effect on the
package leads that will degrade offset voltage and drift. A
shield or cover that prevents air currents from flowing near
the INA101 will assure best performance.
FIGURE 2. Optional Trimming of Input and Output Offset Voltage.
A
1
A
2
A
3
8
7
10kΩ10kΩ
10kΩ10kΩ
2
9
5
4
1
10
R
G
No
Connection
+15V
INA101
Output
20kΩ
20kΩ
3
–15V
6
TO-100 PACKAGE
E
1
V
O
= G (E
1
– E
2
)
Tantalum
1µF
+
Tantalum
1µF
+
E
2
G = 1 + 40kΩ
R
G
FIGURE 1. Basic Connections.
TEXAS INSTRUMENTS Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
INA101AG NRND CDIP SB JD 14 1 RoHS & Green AU N / A for Pkg Type INA101AG
INA101AM NRND TO-100 LME 10 20 RoHS & Green Call TI N / A for Pkg Type INA101AM
INA101CM NRND TO-100 LME 10 20 RoHS & Green Call TI N / A for Pkg Type INA101CM
INA101HP ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 INA101HP
INA101HPG4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 INA101HP
INA101KU ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR INA101KU
INA101KU/1K ACTIVE SOIC DW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR INA101KU
INA101KUE4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR INA101KU
INA101SM NRND TO-100 LME 10 20 RoHS & Green AU N / A for Pkg Type INA101SM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
INA101KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA101KU/1K SOIC DW 16 1000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
INA101AG JD CDIP SB 14 1 506.98 15.24 12290 NA
INA101AM LME TO-CAN 10 20 532.13 21.59 889 NA
INA101CM LME TO-CAN 10 20 532.13 21.59 889 NA
INA101HP N PDIP 14 25 506 13.97 11230 4.32
INA101HPG4 N PDIP 14 25 506 13.97 11230 4.32
INA101KU DW SOIC 16 40 507 12.83 5080 6.6
INA101KUE4 DW SOIC 16 40 507 12.83 5080 6.6
INA101SM LME TO-CAN 10 20 532.13 21.59 889 NA
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 3
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