CD54,74HC(T)173 Datasheet by Texas Instruments

U Ordering & Technical Design a 3 Support 5 o . quahly documentation development (raming ' TEXAS INSTRUMENTS
CDx4HC173, CDx4HCT173 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-
State
1 Features
• Three-state buffered outputs
• Gated input and output enables
• Fanout (over temperature range)
– Standard outputs : 10 LSTTL loads
– Bus driver outputs : 15 LSTTL loads
• Wide Operating Temperature Range : -55°C to
125°C
• Balanced propagation delay and transition times
• Significant power and reduction compared to
LSTTL logic ICs
• HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
• HCT types
– 4.5 V to 5.5 V Operation
– Direct LSTTL input logic compatibility, VIL= 0.8
V (Max), VIH = 2 V (Min)
– CMOS input compatibility, Il ≤ 1µA at VOL, VOH
2 Description
The CDx4HC173 and CDx4HCT173 contains four
independent D-type flip-flops with shared clock (CP),
reset (MR), and data enable (E1, E2) pins.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD54HC173F CDIP (16) 21.34 mm × 6.92 mm
CD54HCT173F3A CDIP (16) 21.34 mm × 6.92 mm
CD74HC173E PDIP (16) 19.31mm × 6.35 mm
CD74HCT173E PDIP (16) 19.31mm × 6.35 mm
CD74HC173M SOIC (16) 9.90 mm × 3.90 mm
CD74HCT173M SOIC (16) 9.90 mm × 3.90 mm
CD74HC173PW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all packages see the orderable addendum at the end of
the data sheet..
E1
E2
Dx
CP
MR
OE1
OE2
QxD
R
Q
Shared Control Logic
One of Four D-Type Flip-Flops
Functional Block Diagram
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings ....................................... 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics............................................6
5.6 Prerequisite For Switching Characteristics................. 7
6 Parameter Measurement Information............................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................11
8 Power Supply Recommendations................................12
9 Layout.............................................................................12
9.1 Layout Guidelines..................................................... 12
10 Device and Documentation Support..........................13
10.1 Documentation Support.......................................... 13
10.2 Receiving Notification of Documentation Updates..13
10.3 Support Resources................................................. 13
10.4 Trademarks.............................................................13
10.5 Electrostatic Discharge Caution..............................13
10.6 Glossary..................................................................13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 13
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2003) to Revision F (March 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
2Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
l TEXAS INSTRUMENTS
4 Pin Configuration and Functions
J, N, D, or PW Package
16-Pin CDIP, PDIP, SOIC, or TSSOP
Top View
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
TEXAS INSTRUMENTS
5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input diode current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output diode current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IOOutput source or sink current per output pin VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
Continuous current through VCC or GND ±70 mA
TJJunction temperature 150 °C
Lead temperature (soldering 10s) (SOIC - lead tips only) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions
MIN MAX UNIT
VCC Supply voltage range HC types 2 6 V
HCT types 4.5 5.5
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
ttInput rise and fall time
VCC = 2V 1000
nsVCC = 4.5V 500
VCC = 6V 400
TATemperature range -55 125 °C
5.3 Thermal Information
THERMAL METRIC
N (PDIP) D (SOIC) NS (SOP) PW (TSSOP)
UNIT16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal
resistance(1) 67 73 64 108 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
4Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
TEXAS INSTRUMENTS
5.4 Electrical Characteristics
PARAMETER TEST
CONDITIONS(1) VCC
25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VIH High-level input voltage
2 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15 V
6 4.2 4.2 4.2 V
VIL Low-level input voltage
2 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8 V
VOH
High-level output voltage
CMOS loads
IOH = – 20μA 2 1.9 1.9 1.9 V
IOH = – 20μA 4.5 4.4 4.4 4.4 V
IOH = – 20μA 6 5.9 5.9 5.9 V
High-level output voltage
TTL loads
IOH = – 6mA 4.5 3.98 3.84 3.7 V
IOH = – 7.8mA 6 5.48 5.34 5.2 V
VOL
Low-level output voltage
CMOS loads
IOL = 20μA 2 0.1 0.1 0.1 V
IOL = 20μA 4.5 0.1 0.1 0.1 V
IOL = 20μA 6 0.1 0.1 0.1 V
Low-level output voltage
TTL loads
IOL = 6mA 4.5 0.26 0.33 0.4 V
IOL = 7.8mA 6 0.26 0.33 0.4 V
IIInput leakage current VCC or GND 6 ±0.1 ±1 ±1 µA
ICC Supply current VCC or GND 6 8 80 160 µA
IOZ
Three-state leakage
current 6 ±0.5 ±0.5 ±10 µA
HCT TYPES
VIH High-level input voltage 4.5 to
5.5 2 2 2 V
VIL Low-level input voltage 4.5 to
5.5 0.8 0.8 0.8 V
VOH
High-level output voltage
CMOS loads IOH = – 20μA 4.5 4.4 4.4 4.4 V
High-level output voltage
TTL loads IOH = – 6mA 4.5 3.98 3.84 3.7 V
VOL
Low-level output voltage
CMOS loads IOL = 20μA 4.5 0.1 0.1 0.1 V
Low-level output voltage
TTL loads IOL = 6mA 4.5 0.26 0.33 0.4 V
IIInput leakage current VCC and GND 5.5 ±0.1 ±1 ±1 µA
ICC Supply Current VCC and GND 5.5 8 80 160 µA
∆ICC (2) (3) Additional supply current
per input pin
One of D0-D3 4.5 to
5.5 15 54 67.5 73.5 µA
One of E1 and
E2
4.5 to
5.5 15 54 67.5 73.5 µA
CP 4.5 to
5.5 25 90 112.5 122.5 µA
MR 4.5 to
5.5 20 72 90 98 µA
One of OE1 and
OE2
4.5 to
5.5 50 180 225 245 µA
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
TEXAS INSTRUMENTS
PARAMETER TEST
CONDITIONS(1) VCC
25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
IOZ
Three-state leakage
current 5.5 ±0.5 ±5.0 ±10 µA
(1) VI = VIH or VIL, unless otherwise noted.
(2) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
(3) Inputs held at VCC – 2.1.
5.5 Switching Characteristics
Input tt = 6ns. Unless otherwise specified, CL = 50pF
PARAMETER VCC(V) 25°C -40°C to
85°C
-55°C to
125°C UNIT
TYP MAX MAX MAX
HC TYPES
tpd
Propagation delay, clock to
output
2 200 250 300
ns4.5 17(1) 40 50 60
6 34 43 51
tpd Propagation delay, MR to output
2 175 220 265
ns4.5 12(1) 35 44 53
6 30 37 45
tpd
Propagation delay output enable
to Q (Figure 6)
2 150 190 225
ns4.5 12(1) 30 38 45
6 26 33 38
ttOutput transition times
2 60 75 90
ns4.5 12 15 18
6 10 13 15
fMAX Maximum clock frequency 5 60(1) MHz
CiInput capacitance 10 10 10 pF
COThree-state output capacitance 10 10 10 pF
Cpd (2) (3) Power dissipation capacitance 5 29 pF
HCT TYPES
tpd
Propagation delay, clock to
output 4.5 17(1) 40 50 60 ns
tpd Propagation delay, MR to output 4.5 18(1) 44 55 66 ns
tpd
Propagation delay output enable
to Q (Figure 6)
2 150 190 225
ns4.5 14(1) 30 38 45
6 26 33 38
ttOutput transition times 4.5 15 19 22 ns
fMAX Maximum clock frequency 5 60(1) MHz
CiInput capacitance 10 10 10 pF
Cpd (2) (3) Power dissipation capacitance 5 34 pF
(1) Typical value tested at 5V, CL = 15pF.
(2) CPD is used to determine th edynamic power consumption, per package.
(3) PD = VCC 2fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
6Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
TEXAS INSTRUMENTS
5.6 Prerequisite For Switching Characteristics
PARAMETER VCC(V) 25°C -40°C to 85°C -55°C to 125°C UNITS
MIN MAX MIN MAX MIN MAX
HC TYPES
fMAX Maximum clock frequency
2 6 5 4
MHz4.5 30 24 20
6 35 28 24
tWMR pulse width
2 80 100 120
ns4.5 16 20 24
6 14 17 20
tWClock pulse width
2 80 100 120
ns4.5 16 20 24
6 14 17 20
tSU
Set-up time, data to clock and
E to clock
2 60 75 90
ns4.5 12 15 18
6 10 13 15
tHHold time, data to clock
2 3 3 3
ns4.5 3 3 3
6 3 3 3
tHHold time, E to clock
2 0 0 0
ns4.5 0 0 0
6 0 0 0
tREM Removal time, MR to clock
2 60 75 90
ns4.5 12 15 18
6 10 13 15
HCT TYPES
fMAX Maximum clock frequency 4.5 20 16 13 MHz
tWtWMR pulse width 4.5 15 19 22 ns
tWClock pulse width 4.5 25 31 38 ns
tSU Set-up Time, E to clock 4.5 12 15 18 ns
tSU Set-up time, data to clock 4.5 18 23 27 ns
tHHold time, data to clock 4.5 0 0 0 ns
tHHold time, E to clock 4.5 0 0 0 ns
tREM Removal time, MR to clock 4.5 12 15 18 ns
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
I TEXAS INSTRUMENTS v, = (ins + = (ins a t " v 3v CC INPUT Input GND GMD 'vHL INVERTING IMVERTING Gum” ouTPur +
6 Parameter Measurement Information
tPD is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL
NOTE: Outputs should be switching from 10% VCC to
90% VCC in accordance with device truth table. For
fMAX, input duty cycle = 50%
Figure 6-1. HC clock pulse rise and fall times and
pulse width
NOTE: Outputs should be switching from 10% VCC to
90% VCC in accordance with device truth table. FOr
fMAX, input duty cycle = 50%
Figure 6-2. HCT clock pulse rise and fall times and
pulse width
Figure 6-3. HC and HCU transition times and
propagation delay times, combination logic
Figure 6-4. HCT transition times and propagation
delay times, combination logic
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
8Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
I TEXAS INSTRUMENTS Vcc GND OUTPUT Vcc sET, RESET 0R PRESET GND Ill—L cl 5an (ins a e « Gns Vcc OUTPUT DISABLE DUTPUI Low to OFF 1.3V 'SUIU .— 'WL 90% ouwuv 3v SET. RESET 0R PRESET GND GND Ira «Hm I a‘ «Bus ouTPuI 2.7 DISABLE — GND OUTPUT Low TO OFF OUTPUT HIGII OUTPUT HIGH to on 5”" T0 OFF 1.3V oumns a ouTPuTs fi ouqus OuTPUTS , OUTPUTS at OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED O'NER °' ouTPuI INPUTS 0- n: wmI BL kn TIED HIGH 0- mREE. Vcc FOR M1 AND Im DR Low 9- smE CL GND son xmz AND [pm 0mm” 0- ouwur 159p; DISABLE -
Figure 6-5. HC setup times, hold times, removal
time, and propagation delay times for edge
triggered sequential logic circuits
Figure 6-6. HCT setup times, hold times, removal
time, and propagation delay times for edge
triggered sequential logic circuits
Figure 6-7. HC three-state propagation delay
waveform
Figure 6-8. HCT three-state propagation delay
waveform
NOTE: Opend drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test
circuit is Output RL = 1kΩ to VCC, CL = 50pF
Figure 6-9. HC and HCT three-state propagation delay test circuit
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
STRUMENTS
7 Detailed Description
7.1 Overview
The CDx4HC173 or CDx4HCT173 high speed three-state quad Dtype flip-flops are fabricated with silicon gate
CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive
15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for
interfacing with bus lines in bus oriented systems
The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode
when either of the two output disable pins are at the logic “1” level. The input ENABLES allow the flip-flops to
remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a
logic “1” level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is
enabled by taking the RESET (MR) input to a logic “1” level. The data outputs change state on the positive going
edge of the clock.
The ’HCT173 logic family is functionally, as well as pin compatible with the standard LS logic family.
7.2 Functional Block Diagram
E1
E2
Dx
CP
MR
OE1
OE2
QxD
R
Q
Shared Control Logic
One of Four D-Type Flip-Flops
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
I TEXAS INSTRUMENTS
7.3 Device Functional Modes
Table 7-1. Truth Table(1)(2)
INPUTS DATA OUTPUT
MR CP DATA ENABLE
E1 E2 D Qn
H X X X X L
L L X X X Q0
L ↑ H X X Q0
L ↑ X H X Q0
L ↑ L L L L
L ↑ L L H H
(1) H = High voltage level. L = Low voltage level. X = Irrelevant. ↑ =
Transition from low to high level. Q0 = Level before the indicated
steady-state input conditions were established.
(2) When either OE1 or OE2 (or both) is (are) high, the output
is disabled to the high-impedance stat, however, sequential
operation of the flip-flops is not affected.
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
I TEXAS INSTRUMENTS
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com
12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
l TEXAS INSTRUMENTS
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13
Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8682501EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8682501EA
CD54HC173F3A Samples
5962-8875901EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8875901EA
CD54HCT173F3A Samples
CD54HC173F ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HC173F Samples
CD54HC173F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8682501EA
CD54HC173F3A Samples
CD54HCT173F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8875901EA
CD54HCT173F3A Samples
CD74HC173E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC173E Samples
CD74HC173M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M Samples
CD74HC173M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M Samples
CD74HC173M96G4 ACTIVE SOIC D 16 2500 TBD Call TI Call TI -55 to 125 Samples
CD74HC173MG4 ACTIVE SOIC D 16 40 TBD Call TI Call TI -55 to 125 Samples
CD74HC173PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 Samples
CD74HC173PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 Samples
CD74HCT173E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT173E Samples
CD74HCT173M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M Samples
CD74HCT173M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M Samples
CD74HCT173MG4 ACTIVE SOIC D 16 40 TBD Call TI Call TI -55 to 125 Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC173, CD54HCT173, CD74HC173, CD74HCT173 :
•Catalog : CD74HC173, CD74HCT173
•Military : CD54HC173, CD54HCT173
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC173M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC173PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT173M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC173M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC173PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT173M96 SOIC D 16 2500 340.5 336.1 32.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC173E N PDIP 16 25 506 13.97 11230 4.32
CD74HC173E N PDIP 16 25 506 13.97 11230 4.32
CD74HC173M D SOIC 16 40 507 8 3940 4.32
CD74HC173PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HCT173E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT173E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT173M D SOIC 16 40 507 8 3940 4.32
Pack Materials-Page 3
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated