TCAN1042 Datasheet by Texas Instruments

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TCAN1042 Fault Protected CAN Transceiver with CAN FD

1 Features

• Meets the ISO 11898-2:2016 and

ISO 11898-5:2007 physical layer standards

• 'Turbo' CAN:

– All devices support classic CAN and 2 Mbps

CAN FD (flexible data rate) and "G" options

support 5 Mbps

– Short and symmetrical propagation delay times

and fast loop times for enhanced timing margin

– Higher data rates in loaded CAN networks

• I/O Voltage range supports 3.3 V and 5 V MCUs

• Ideal passive behavior when unpowered

– Bus and logic terminals are high impedance

(no load)

– Power up/down with glitch free operation on

bus and RXD output

• Protection features

– HBM ESD protection: ±16 kV

– IEC ESD protection up to ±15 kV

– Bus Fault protection: ±58 V (non-H variants)

and ±70 V (H variants)

– Undervoltage protection on VCC and VIO

(V variants only) supply terminals

– Driver dominant time out (TXD DTO) - Data

rates down to 10 kbps

– Thermal shutdown protection (TSD)

• Receiver common mode input voltage: ±30 V

• Typical loop delay: 110 ns

• Junction temperatures from –55°C to 150°C

• Available in SOIC(8) package and leadless VSON

(8) package (3.0 mm x 3.0 mm) with improved

automated optical inspection (AOI) capability

2 Applications

•All devices support highly loaded CAN networks

• Heavy machinery ISOBUS applications –

ISO 11783

•Industrial automation, control, sensors and drive

systems

•Building, security and climate control automation

•Telecom base station status and control

• CAN Bus standards such as CANopen,

DeviceNet, NMEA2000, ARNIC825, ISO11783,

CANaerospace

3 Description

This CAN transceiver family meets the ISO11898-2

(2016) High Speed CAN (Controller Area Network)

physical layer standard. All devices are designed for

use in CAN FD networks up to 2 Mbps (megabits

per second). Devices with part numbers that include

the "G" suffix are designed for data rates up to 5

Mbps, and versions with the "V" have a secondary

power supply input for I/O level shifting the input

pin thresholds and RXD output level. This family

has a low power standby mode with remote wake

request feature. Additionally, all devices include many

protection features to enhance device and network

robustness.

Device Information

PART NUMBER PACKAGE(1) BODY SIZE

TCAN1042x SOIC (8) 4.90 mm × 3.91 mm

VSON (8) 3.00 mm x 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TSD

UVP

Mode Select

Logic Output

TXD

STB

RXD

CANH

CANL

GND

NC or VIO

VCC

VCC or VIO

Dominant

time-out

VCC or VIO

WUP Monitor

MUX

Low Power Receiver

A. Terminal 5 function is device dependent; NC on devices

without the "V" suffix, and VIO for I/O level shifting for devices

with the "V" suffix.

B. RXD logic output is driven to VCC on devices without the "V"

suffix, and VIO for devices with the "V" suffix.

Functional Block Diagram

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configurations and Functions.................................5

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings............................................................... 6

7.3 ESD Ratings, Specifications....................................... 7

7.4 Recommended Operating Conditions.........................8

7.5 Thermal Information....................................................8

7.6 Power Rating.............................................................. 8

7.7 Electrical Characteristics.............................................9

7.8 Switching Characteristics..........................................12

7.9 Typical Characteristics.............................................. 13

8 Parameter Measurement Information.......................... 14

9 Detailed Description......................................................18

9.1 Overview................................................................... 18

9.2 Functional Block Diagram......................................... 18

9.3 Feature Description...................................................19

9.4 Device Functional Modes..........................................22

10 Application and Implementation................................ 26

10.1 Application Information........................................... 26

10.2 Typical Applications................................................ 26

11 Power Supply Recommendations..............................29

12 Device and Documentation Support..........................32

12.1 Receiving Notification of Documentation Updates..32

12.2 Support Resources................................................. 32

12.3 Trademarks.............................................................32

12.4 Electrostatic Discharge Caution..............................32

12.5 Glossary..................................................................32

13 Mechanical, Packaging, and Orderable

Information.................................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April 2017) to Revision D (October 2021) Page

• Deleted devices: TCAN1042, TCAN1042G, TCAN1042GV, and TCAN1042V ................................................. 1

• Added footnote to the GND pin in the Pin Functions table ................................................................................ 5

• Changed the DRB (VSON) values in the Thermal Information table .................................................................8

• Changed the title in Section 9.3.7.1 .................................................................................................................21

• Changed the title in Section 9.3.7.2 .................................................................................................................21

Changes from Revision B (August 2016) to Revision C (April 2017) Page

• Deleted Feature "Meets the December 17th, 2015 Draft of ISO 11898-2 Physical Layer Update".................... 1

• Changed Feature From: "Meets the Released ISO 11898-2:2007 and ISO 11898-2:2003 Physical Layer

Standards" To: "Meets the ISO 11898-2:2016 and ISO 11898-5:2007 Physical Layer Standards"....................1

• Changed Feature From: "All devices support 2 Mbps CAN FD.." To: "All Devices Support Classic CAN and 2

Mbps CAN FD.."................................................................................................................................................. 1

• Changed Charged Device Model (CDM) From: ±750 To: ±1500 in the ESD Ratings table................................6

• Changed TBD to values for the DRB (VSON) Package in the ESD Ratings table............................................. 6

• Added the Power Rating table ........................................................................................................................... 8

• Changed VSYM in the Driver Electrical Characteristics table.............................................................................. 9

• Changed VSYM_DC in the Driver Electrical Characteristics table......................................................................... 9

• Deleted "VI = 0.4 sin (4E6 π t) + 2.5 V" from the Test Condition of CI in the Receiver Electrical Characteristics

table.................................................................................................................................................................... 9

• Deleted "VI = 0.4 sin (4E6 π t)" in the Test Condition of CID in the Receiver Electrical Characteristics table.....9

• Added "-30 V ≤ VCM ≤ +30" to the Test Condition of RID and RIN in the Receiver Electrical Characteristics

table.................................................................................................................................................................... 9

• Added Note 2 and Changed Table 9-2, BUS OUTPUT column........................................................................20

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TCAN1042HGV, TCAN1042HV

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Changes from Revision A (May 2016) to Revision B (August 2016) Page

• Added devices: TCAN1042, TCAN1042G, TCAN1042GV, and TCAN1042V ................................................... 1

• Changed Feature From: Added Bus Fault Protection: ±70 V To: Bus Fault Protection: ±58 V (non-H variants)

and ±70 V (H variants)........................................................................................................................................1

• Added Feature "Available in SOIC(8) package and leadless VSON(8) package..."...........................................1

• Added new devices to the Device Comparison Table ........................................................................................4

• Added the DRB package to the Thermal Information table ............................................................................... 8

• Changed the tMODE TYP value From: 1 µs To: 9 µS in the Switching Characteristics table............................. 12

• Changed Standby Mode section ......................................................................................................................23

Changes from Revision * (March 2016) to Revision A (May 2016) Page

• Added the VSON (8) pin package to the Device Information table.....................................................................1

• Added the VSON (8) pin package to the Pin Configuration and Functions ....................................................... 5

• Changed OTP to TSD in the Functional Block Diagram ..................................................................................18

• Added Note 2 to Table 9-1 ............................................................................................................................... 20

• Added Note 1 to Table 9-2 ............................................................................................................................... 20

• Added pin number to the Layout Example image ............................................................................................31

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5 Device Comparison Table

DEVICE

NUMBER BUS FAULT PROTECTION 5-Mbps FLEXIBLE DATA

RATE

3-V LEVEL SHIFTER

INTEGRATED PIN 8 MODE SELECTION

TCAN1042 (Base) ±58 V

Low Power Standby Mode

with Remote Wake

TCAN1042G ±58 V X

TCAN1042GV ±58 V X X

TCAN1042V ±58 V X

TCAN1042H ±70 V

TCAN1042HG ±70 V X

TCAN1042HGV ±70 V X X

TCAN1042HV ±70 V X

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6 Pin Configurations and Functions

TXD

RXD

GND

VCC

STB

CANH

CANL

Figure 6-1. D Package for Base, (H), (G) and (HG)

Devices8 PIN (SOIC) Top View

TXD

RXD

GND

VCC

STB

CANH

CANL

Figure 6-2. DRB Package for Base, (H), (G) and

(HG) Devices 8 PIN (VSON) Top View

TXD

RXD

GND

VCC

STB

CANH

CANL

VIO

Figure 6-3. D Package for (V), (HV), (GV), and

(HGV) Devices 8 PIN (SOIC) Top View

TXD

RXD

GND

VCC

STB

CANH

CANL

VIO

Figure 6-4. DRB Package for (V), (HV), (GV), and

(HGV) Devices 8 PIN (VSON) Top View

Table 6-1. Pin Functions

PINS

TYPE DESCRIPTION

NAME (H), (G), (HG) (V), (GV), (HV),

(HGV)

TXD 1 1 DIGITAL INPUT CAN transmit data input (LOW for dominant and HIGH for recessive bus states)

GND(1) 2 2 GND Ground connection

VCC 3 3 POWER Transceiver 5-V supply voltage

RXD 4 4 DIGITAL OUTPUT CAN receive data output (LOW for dominant and HIGH for recessive bus states)

NC 5 — — No Connect

VIO — 5 POWER Transceiver I/O level shifting supply voltage (Devices with "V" suffix only)

CANL 6 6 BUS I/O Low level CAN bus input/output line

CANH 7 7 BUS I/O High level CAN bus input/output line

STB 8 8 DIGITAL INPUT Standby Mode control input (active high)

(1) For DRB (VSON) package options, the thermal pad may be connected to GND in order to optimize the thermal characteristics of the

package.

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7 Specifications

over operating free-air temperature range (unless otherwise noted) (1) (2)

7.1 Absolute Maximum Ratings

MIN MAX UNIT

VCC 5-V Bus Supply Voltage Range All Devices –0.3 7 V

VIO I/O Level-Shifting Voltage Range Devices with the "V" Suffix –0.3 7 V

VBUS

CAN Bus I/O voltage range (CANH,

CANL) Devices with the "H" Suffix -70 70 V

V(Logic_Input)

Logic input terminal voltage range (TXD,

All Devices

–0.3 +7 and VI ≤ VIO + 0.3 V

V(Logic_Output) Logic output terminal voltage range (RXD) –0.3 +7 and VI ≤ VIO + 0.3 V

IO(RXD) RXD (Receiver) output current –8 8 mA

TJVirtual junction temperature range (see Thermal Information table) –55 150 °C

TSTG Storage temperature range (see Thermal Information table) –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

7.2 ESD Ratings

TEST CONDITIONS VALUE UNIT

D (SOIC) Package

Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V

CAN bus terminals (CANH, CANL) to GND(2) ±16000

Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V

Machine Model (MM) All terminals(4) ±200

DRB (VSON) Package

Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V

CAN bus terminals (CANH, CANL) to GND(2) ±16000

Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V

Machine Model (MM) All terminals(4) ±200

(1) Tested in accordance to JEDEC Standard 22, Test Method A114.

(2) Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND.

(3) Tested in accordance to JEDEC Standard 22, Test Method C101.

(4) Tested in accordance to JEDEC Standard 22, Test Method A115.

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TCAN1042HGV, TCAN1042HV

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7.3 ESD Ratings, Specifications

TEST CONDITIONS VALUE UNIT

D (SOIC) Package

System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH,

CANL) to GND

IEC 61000-4-2: Unpowered

Contact Discharge ±15000

IEC 61000-4-2: Powered on

Contact Discharge ±8000

System Level Electrical fast transient (EFT) CAN bus terminals (CANH,

CANL) to GND IEC 61000-4-4: Criteria A ±4000 V

DRB (VSON) Package

System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH,

CANL) to GND

IEC 61000-4-2: Unpowered

Contact Discharge ±14000

IEC 61000-4-2: Powered on

Contact Discharge ±8000

System Level Electrical fast transient (EFT) CAN bus terminals (CANH,

CANL) to GND IEC 61000-4-4: Criteria A ±4000 V

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TCAN1042HGV, TCAN1042HV

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7.4 Recommended Operating Conditions

MIN MAX UNIT

VCC 5-V Bus Supply Voltage Range 4.5 5.5 V

VIO I/O Level-Shifting Voltage Range 3 5.5

IOH(RXD) RXD terminal HIGH level output current –2 mA

IOL(RXD) RXD terminal LOW level output current 2

7.5 Thermal Information

Thermal Metric(1) TEST CONDITIONS

TCAN1042

UNITD (SOIC) DRB (VSON)

8 Pins 8 Pins

RθJA Junction-to-air thermal resistance High-K thermal resistance(2) 105.8 48.3 °C/W

RθJB Junction-to-board thermal resistance(3) 46.8 17.2 °C/W

RθJC(TOP)

Junction-to-case (top) thermal

resistance(4) 48.3 37.6 °C/W

ΨJT

Junction-to-top characterization

parameter(5) 8.7 1.8 °C/W

ΨJB

Junction-to-board characterization

parameter(6) 46.2 17.1 °C/W

TTSD Thermal shutdown temperature 170 170 °C

TTSD_HYS Thermal shutdown hysteresis 5 5 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,

as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.6 Power Rating

PARAMETER TEST CONDITIONS POWER DISSIPATION UNIT

PDAverage power dissipation

VCC = 5 V, VIO = 5 V (if applicable), TJ = 27°C, RL = 60 Ω,

S at 0 V, Input to TXD at 250 kHz, CL_RXD = 15 pF. Typical

CAN operating conditions at 500 kbps with 25% transmission

(dominant) rate.

52 mW

VCC = 5.5 V, VIO = 5.5 V (if applicable), TJ = 150°C, RL = 50 Ω,

S at 0 V, Input to TXD at 500 kHz, CL_RXD = 15 pF. Typical high

load CAN operating conditions at 1 Mbps with 50% transmission

(dominant) rate and loaded network.

124 mW

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7.7 Electrical Characteristics

Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Supply Characteristics

ICC 5-V supply current

Normal mode

(dominant)

See Figure 8-1, TXD = 0 V, RL = 60 Ω,

CL = open, RCM = open, STB = 0 V, Typical

Bus Load

40 70

See Figure 8-1, TXD = 0 V, RL = 50 Ω,

CL = open, RCM = open, STB = 0 V,

High Bus Load

45 80

Normal mode (dominant

– with bus fault)

See Figure 8-1, TXD = 0 V, STB = 0 V,

CANH = -12 V, RL = open, CL = open, RCM =

open

180

Normal mode

(recessive)

See Figure 8-1, TXD = VCC or VIO, RL = 50

Ω, CL = open, RCM = open,

STB = 0 V

1.5 2.5

Standby mode

Devices with the "V" suffix (I/O level-

shifting), VCC not needed in Standby mode,

See Figure 8-1,

TXD = VIO, RL = 50 Ω, CL = open,

RCM = open, STB = VIO

0.5 5

µA

Devices without the "V" suffix (5-V only),

See Figure 8-1, TXD = VCC, RL = 50 Ω, CL =

open, RCM = open, STB = VCC

IIO I/O supply current

Normal mode RXD floating, TXD = STB = 0 or 5.5 V 90 300

Standby mode RXD floating, TXD = STB = VIO,

VCC = 0 or 5.5 V 12 17

UVVCC

Rising undervoltage detection on VCC for

protected mode

All devices

4.2 4.4

Falling undervoltage detection on VCC for

protected mode 3.8 4.0 4.25

VHYS(UVVCC) Hysteresis voltage on UVVCC 200 mV

UVVIO

Undervoltage detection on VIO for protected

mode Devices with the "V" suffix (I/O level-shifting) 1.3 2.75 V

VHYS(UVVIO) Hysteresis voltage on UVVIO for protected mode 80 mV

STB Terminal (Mode Select Input)

VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO

Devices without the "V" suffix (5-V only) 2

VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO

Devices without the "V" suffix (5-V only) 0.8

IIH High-level input leakage current STB = VCC = VIO = 5.5 V -2 2

µAIIL Low-level input leakage current STB = 0V, VCC = VIO = 5.5 V –20 0 -2

Ilkg(OFF) Unpowered leakage current STB = 5.5 V, VCC = VIO = 0 V -1 0 1

TXD Terminal (CAN Transmit Data Input)

VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO

Devices without the "V" suffix (5-V only) 2

VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO

Devices without the "V" suffix (5-V only) 0.8

IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1

µAIIL Low-level input leakage current TXD = 0 V, VCC = VIO = 5.5 V –100 -25 –7

Ilkg(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 0 1

CIInput capacitance VIN = 0.4 x sin(2 x π x 2 x 106 x t) + 2.5 V 5 pF

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7.7 Electrical Characteristics (continued)

Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

RXD Terminal (Can Receive Data Output)

VOH High-level output voltage

Devices with the "V" suffix (I/O level-

shifting), See Figure 8-2,

IO = –2 mA.

0.8 × VIO

Devices without the "V" suffix

(5V only), See Figure 8-2,

IO = –2 mA.

4 4.6

VOL Low-level output voltage

Devices with the "V" suffix (I/O level-

shifting), See Figure 8-2, IO = +2 mA. 0.2 x VIO

Devices without the "V" suffix (5-V only),

See Figure 8-2,

IO = +2 mA.

0.2 0.4

Ilkg(OFF) Unpowered leakage current RXD = 5.5 V, VCC = 0 V, VIO = 0 V –1 0 1 µA

Driver Electrical Characteristics

VO(DOM)

Bus output voltage

(dominant)

CANH See Figure 8-1 and Figure 9-3, TXD = 0 V,

STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω,

CL = open, RCM = open

2.75 4.5

CANL 0.5 2.25

VO(REC)

Bus output voltage

(recessive) CANH and CANL

See Figure 8-1 and Figure 9-3, TXD = VCC

or VIO, VIO = VCC, STB = 0 V ,

RL = open (no load), RCM = open

2 0.5 × VCC 3

VO(STB)

Bus output voltage

(Standby mode)

CANH

See Figure 8-1 and Figure 9-3, STB = VIO,

RL = open (no load), RCM = open

-0.1 0 0.1

CANL -0.1 0 0.1

CANH - CANL -0.2 0 0.2

VOD(DOM)

Differential output

voltage (dominant) CANH - CANL

See Figure 8-1 and Figure 9-3, TXD = 0 V,

STB = 0 V, 45 Ω ≤ RL < 50 Ω,

CL = open, RCM = open

1.4 3

See Figure 8-1 and Figure 9-3, TXD = 0 V,

STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω,

CL = open, RCM = open

1.5 3

See Figure 8-1 and Figure 9-3, TXD = 0 V,

STB = 0 V, RL = 2240 Ω, CL = open, RCM =

open

1.5 5

VOD(REC)

Differential output

voltage (recessive) CANH - CANL

See Figure 8-1 and Figure 9-3, TXD = VCC,

STB = 0 V, RL = 60 Ω, CL = open, RCM =

open

–120 12

See Figure 8-1 and Figure 9-3, TXD = VCC,

STB = 0 V, RL = open (no load), CL = open,

RCM = open

–50 50

VSYM

Output symmetry (dominant or recessive)

( VO(CANH) + VO(CANL)) / VCC

See Figure 8-1 and Figure 10-2, STB at 0 V,

Rterm = 60 Ω, Csplit = 4.7 nF, CL = open,

RCM = open, TXD = 250 kHz, 1 MHz

0.9 1.1 V/V

VSYM_DC

DC Output symmetry (dominant or recessive)

(VCC – VO(CANH) – VO(CANL))

See Figure 8-1 and Figure 9-3, STB = 0 V,

RL = 60 Ω, CL = open, RCM = open –0.4 0.4 V

IOS(SS_DOM)

Short-circuit steady-state output current,

dominant, Normal mode

See Figure 9-3 and Figure 8-7, STB at 0 V,

VCANH = -5 V to 40 V, CANL = open,

TXD = 0 V

–100

See Figure 9-3 and Figure 8-7, STB at 0 V,

VCANL = -5 V to 40 V, CANH = open,

TXD = 0 V

100

IOS(SS_REC)

Short-circuit steady-state output current,

recessive, Normal mode

See Figure 9-3 and Figure 8-7, STB at 0 V,

–27 V ≤ VBUS ≤ 32 V,

Where VBUS = CANH = CANL, TXD = VCC

–5 5 mA

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7.7 Electrical Characteristics (continued)

Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Receiver Electrical Characteristics

VCM Common mode range, Normal mode See Figure 8-2 and Table 8-1, STB = 0 V -30 +30 V

VIT+

Positive-going input threshold voltage, Normal

mode See Figure 8-2, Table 9-5 and Table 8-1,

STB = 0 V, -20 V ≤ VCM ≤ +20 V

900

VIT–

Negative-going input threshold voltage, Normal

mode 500

VIT+

Positive-going input threshold voltage, Normal

mode See Figure 8-2, Table 9-5 and Table 8-1,

STB = 0 V, -30 V ≤ VCM ≤ +30 V

1000

VIT–

Negative-going input threshold voltage, Normal

mode 400

VHYS Hysteresis voltage (VIT+ - VIT–), Normal mode See Figure 8-2, Table 9-5 and Table 8-1,

STB = 0 V 120

VCM Common mode range, Standby mode

Devices with the "V" suffix (I/O level-

shifting), See Figure 8-2, Table 9-5 and

Table 8-1, STB = VIO, 4.5 V ≤ VIO ≤ 5.5 V

-12 12

Devices with the "V" suffix (I/O level-

shifting), See Figure 8-2, Table 9-5 and

Table 8-1, STB = VIO, 3.0 V ≤ VIO ≤ 4.5 V

-2 +7

Devices without the "V" suffix (5V only), See

Figure 8-2, Table 9-5 and Table 8-1, STB =

VCC

-12 12

VIT(STANDBY) Input threshold voltage, Standby mode STB = VCC or VIO 400 1150 mV

ILKG(IOFF) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC = VIO = 0 V 4.8 µA

CIInput capacitance to ground (CANH or CANL) TXD = VCC, VIO = VCC 24 30 pF

CID Differential input capacitance (CANH to CANL) TXD = VCC, VIO = VCC 12 15

RID Differential input resistance TXD = VCC = VIO = 5 V, STB = 0 V,

-30 V ≤ VCM ≤ +30 V

30 80 kΩ

RIN Input resistance (CANH or CANL) 15 40

RIN(M)

Input resistance matching:

[1 – RIN(CANH) / RIN(CANL)] × 100% VCANH = VCANL = 5 V –2% +2%

(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω.

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7.8 Switching Characteristics

Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Device Switching Characteristics

tPROP(LOOP1)

Total loop delay, driver input (TXD) to receiver

output (RXD), recessive to dominant See Figure 8-4, STB = 0 V,

RL = 60 Ω,

CL = 100 pF, CL(RXD) = 15 pF

100 160

tPROP(LOOP2)

Total loop delay, driver input (TXD) to receiver

output (RXD), dominant to recessive 110 175

tMODE

Mode change time, from Normal to Standby or

from Standby to Normal See Figure 8-3 9 45 µs

tWK_FILTER Filter time for valid wake up pattern 0.5 1.85 µs

Driver Switching Characteristics

tpHR

Propagation delay time, high TXD to driver

recessive (dominant to recessive)

See Figure 8-1, STB = 0 V,

RL = 60 Ω,

CL = 100 pF, RCM = open

tpLD

Propagation delay time, low TXD to driver

dominant (recessive to dominant) 55

tsk(p) Pulse skew (|tpHR - tpLD|) 20

tRDifferential output signal rise time 45

tFDifferential output signal fall time 45

tTXD_DTO Dominant timeout See Figure 8-6, STB = 0 V,

RL = 60 Ω, CL = open 1.2 3.8 ms

Receiver Switching Characteristics

tpRH

Propagation delay time, bus recessive input to

high output (Dominant to Recessive)

See Figure 8-2, STB = 0 V,

CL(RXD) = 15 pF

65 ns

tpDL

Propagation delay time, bus dominant input to

low output (Recessive to Dominant) 50 ns

tRRXD Output signal rise time 10 ns

tFRXD Output signal fall time 10 ns

FD Timing Parameters

tBIT(BUS)

Bit time on CAN bus output pins with tBIT(TXD) =

500 ns, all devices

See Figure 8-5 , STB = 0 V,

RL = 60 Ω, CL = 100 pF,

CL(RXD) = 15 pF,

ΔtREC = tBIT(RXD) - tBIT(BUS)

435 530

Bit time on CAN bus output pins with tBIT(TXD) =

200 ns, G device variants only 155 210

tBIT(RXD)

Bit time on RXD output pins with tBIT(TXD) =

500 ns, all devices 400 550

Bit time on RXD output pins with tBIT(TXD) =

200 ns, G device variants only 120 220

ΔtREC

Receiver timing symmetry with tBIT(TXD) = 500

ns, all devices -65 40

Receiver timing symmetry with tBIT(TXD) = 200

ns, G device variants only -45 15

(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω

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7.9 Typical Characteristics

Temperature (°C)

VOD(D) (V)

-55 -35 -15 5 25 45 65 85 105 125

0.5

1.5

2.5

D001

VCC = 5 V VIO = 3.3 V RL = 60 Ω

CL = Open RCM = Open STB = 0 V

Figure 7-1. VOD(D) over Temperature

VCC (V)

VOD(D) (V)

4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

0.5

1.5

2.5

D002

VIO = 5 V STB = 0 V RL = 60 Ω

CL = Open RCM = Open Temp = 25°C

Figure 7-2. VOD(D) over VCC

Temperature (°C)

ICC Recessive (mA)

-55 -35 -15 5 25 45 65 85 105 125

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

D003

VCC = 5 V VIO = 3.3 V RL = 60 Ω

CL = Open RCM = Open STB = 0 V

Figure 7-3. ICC Recessive over Temperature

Temperature (°C)

Total Loop Delay (ns)

-55 -35 -15 5 25 45 65 85 105 125

100

125

150

D004

VCC = 5 V VIO = 3.3 V RL = 60 Ω

CL = 100 pF CL_RXD = 15 pF STB = 0 V

Figure 7-4. Total Loop Delay over Temperature

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8 Parameter Measurement Information

VOD

CANH

CANL

TXD

RCM

VCM

TXD

0.9V

0.5V

VOD

tpLD tpHR

50% 50%

VO(CANH)

VO(CANL)

10%

tRtF

90%

VCC

Figure 8-1. Driver Test Circuit and Measurement

CL_RXD

CANH

RXD

CANL

VID

VID 0.5V

0.9V 1.5V

VO(RXD) 50%

VOH

VOL

tpDL

tpRH

90%

10%

tRtF

Figure 8-2. Receiver Test Circuit and Measurement

Table 8-1. Receiver Differential Input Voltage Threshold Test

INPUT (See Receiver Test Circuit and Measurement OUTPUT

VCANH VCANL |VID| RXD

-29.5 V -30.5 V 1000 mV L

VOL

30.5 V 29.5 V 1000 mV L

-19.55 V -20.45 V 900 mV L

20.45 V 19.55 V 900 mV L

-19.75 V -20.25 V 500 mV H

VOH

20.25 V 19.75 V 500 mV H

-29.8 V -30.2 V 400 mV H

30.2 V 29.8 V 400 mV H

Open Open X H

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CANH

CANL

TXD

VOCL_RXD

RXD

STB

tMODE

STB

RXD

VOH

VOL

VIH

50%

Figure 8-3. tMODE Test Circuit and Measurement

CANH

CANL

TXD

VOCL_RXD

RXD

STB

tPROP(LOOP1)

TXD

RXD

VOH

VOL

VCC

50%

tPROP(LOOP2)

Figure 8-4. TPROP(LOOP) Test Circuit and Measurement

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CANH

CANL

TXD

VOCL_RXD

RXD

STB

5 x tBIT

TXD

VDIFF

70%

500mV

30% 30%

900mV

tBIT(BUS)

RXD

VOH

VOL

70%

30%

tBIT(RXD)

tBIT(TXD)

Figure 8-5. CAN FD Timing Parameter Measurement

VOD

CANH

CANL

TXD

0.9V

0.5V

VOD

VIH

tTXD_DTO

VOD(D)

Figure 8-6. TXD Dominant Timeout Test Circuit and Measurement

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CANH

CANL

TXD

VBUS

IOS

VBUS

200 s

IOS

Figure 8-7. Driver Short Circuit Current Test and Measurement

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9 Detailed Description

9.1 Overview

These CAN transceivers meet the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical

layer standard. They are designed for data rates in excess of 1 Mbps for CAN FD and enhanced timing

margin / higher data rates in long and highly-loaded networks. These devices provide many protection features

to enhance device and CAN robustness.

9.2 Functional Block Diagram

TSD

UVP

Mode Select

Logic Output

TXD

STB

RXD

CANH

CANL

GND

NC or VIO

VCC

VCC or VIO

Dominant

time-out

VCC or VIO

WUP Monitor

MUX

Low Power Receiver

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9.3 Feature Description

9.3.1 TXD Dominant Timeout (DTO)

During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the

transceiver from blocking network communication in the event of a hardware or software failure where TXD

is held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD.

The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This

frees the bus for communication between other nodes on the network. The CAN driver is re-activated when

a recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition. The receiver and RXD

terminal still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD

dominant timeout.

Normal CAN

communication

CAN

Bus

Signal

TXD fault stuck dominant: example PCB

failure or bad software

Fault is repaired & transmission

capability restored

TXD

(driver)

%XVZRXOGEH³VWXFNGRPLQDQW´EORFNLQJFRPPXQLFDWLRQIRUWKH

whole network but TXD DTO prevents this and frees the bus for

communication after the time tTXD_DTO.

tTXD_DTO

Communication from

local node

Communication from

repaired node

RXD

(receiver)

Communication from

other bus node(s)

Communication from

repaired local node

Communication from

other bus node(s)

tTXD_DTO Driver disabled freeing bus for other nodes

Figure 9-1. Example Timing Diagram for TXD DTO

Note

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible

transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive

dominant bits (on TXD) for the worst case, where five successive dominant bits are followed

immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate.

Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO.

9.3.2 Thermal Shutdown (TSD)

If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off

the CAN driver circuits thus blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to

the recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown

condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature

(TTSD_HYS) below the thermal shutdown temperature (TTSD) of the device.

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9.3.3 Undervoltage Lockout

The supply terminals have undervoltage detection that places the device in protected mode. This protects the

bus during an undervoltage event on either the VCC or VIO supply terminals.

Table 9-1. Undervoltage Lockout 5 V Only Devices (Devices without the "V" Suffix)

VCC DEVICE STATE(1) BUS OUTPUT RXD

> UVVCC Normal Per TXD Mirrors Bus(2)

< UVVCC Protected High Impedance High Impedance

(1) See the VIT section of the Electrical Characteristics.

(2) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

Table 9-2. Undervoltage Lockout I/O Level Shifting Devices (Devices with the "V" Suffix)

VCC VIO DEVICE STATE BUS OUTPUT RXD

> UVVCC > UVVIO Normal Per TXD Mirrors Bus(1)

< UVVCC > UVVIO

STB = High: Standby Mode Recessive Bus Wake RXD Request(2)

STB =Low: Protected

Mode High Impedance High (Recessive)

> UVVCC < UVVIO Protected High Impedance High Impedance

< UVVCC < UVVIO Protected High Impedance High Impedance

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

(2) Refer to Section 9.4.3.1

Note

After an undervoltage condition is cleared and the supplies have returned to valid levels, the device

typically resumes normal operation within 50 µs.

9.3.4 Unpowered Device

The device is designed to be 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus terminals

(CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the

bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in

operation. The logic terminals also have extremely low leakage currents when the device is unpowered to avoid

loading down other circuits that may remain powered.

9.3.5 Floating Terminals

These devices have internal pull ups on critical terminals to place the device into known states if the terminals

float. The TXD terminal is pulled up to VCC or VIO to force a recessive input level if the terminal floats. The STB

terminal is also pulled up to force the device into low power Standby mode if the terminal floats.

9.3.6 CAN Bus Short Circuit Current Limiting

The device has two protection features that limit the short circuit current when a CAN bus line is short-circuit

fault condition: driver current limiting (both dominant and recessive states) and TXD dominant state time out

to prevent permanent higher short circuit current of the dominant state during a system fault. During CAN

communication the bus switches between dominant and recessive states, thus the short circuit current may be

viewed either as the instantaneous current during each bus state or as an average current of the two states. For

system current (power supply) and power considerations in the termination resistors and common-mode choke

ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data

in the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at

certain times:

• Control fields with set bits

• Bit stuffing

• Interframe space

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• TXD dominant time out (fault case limiting)

These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage

of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their

respective short circuit currents. The average short circuit current may be calculated with the following formula:

IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC](1)

Where:

• IOS(AVG) is the average short circuit current

• %Transmit is the percentage the node is transmitting CAN messages

• %Receive is the percentage the node is receiving CAN messages

• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages

• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages

• IOS(SS)_REC is the recessive steady state short circuit current

• IOS(SS)_DOM is the dominant steady state short circuit current

Note

Consider the short circuit current and possible fault cases of the network when sizing the power

ratings of the termination resistance and other network components.

9.3.7 Digital Inputs and Outputs

9.3.7.1 Devices with VCC Only (Devices without the "V" Suffix):

The 5-V VCC only devices are supplied by a single 5-V rail. The digital inputs have TTL input thresholds and are

therefore 5 V and 3.3 V compatible. The RXD outputs on these devices are driven to the VCC rail for logic high

output. Additionally, the TXD and STB pins are internally pulled up to VCC. The internal bias of the mode pins

may only place the device into a known state if the terminals float, they may not be adequate for system-level

biasing during transients or noisy environments.

Note

TXD pull up strength and CAN bit timing require special consideration when these devices are used

with CAN controllers with an open-drain TXD output. An adequate external pull up resistor must be

used to ensure that the CAN controller output of the microcontroller maintains adequate bit timing to

the TXD input.

9.3.7.2 Devices with VIO I/O Level Shifting (Devices with "V" Suffix):

These devices use a 5 V VCC power supply for the CAN driver and high speed receiver blocks. These

transceivers have a second power supply for I/O level-shifting (VIO). This supply is used to set the CMOS

input thresholds of the TXD and pins and the RXD high level output voltage. Additionally, the internal pull ups on

TXD and STB are pulled up to VIO.

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l TEXAS INSTRUMENTS \ Nwmal Mode \ Standby Mode \ G) \ E CANH ‘ E w > w \ 3 £0 E \ U a \ ,f w \ \ ‘ 1 ‘ Recesswe} Dominant fRecesswe: >Time.t CANH 25v A Bwas RXD um GNDJP :: CANL «M, A: Normal Modes B: Standby Mode (Low Power)

9.4 Device Functional Modes

The device has two main operating modes: Normal mode and Standby mode. Operating mode selection is made

via the STB input terminal.

Table 9-3. Operating Modes

STB Terminal MODE DRIVER RECEIVER RXD Terminal

LOW Normal Mode Enabled (ON) Enabled (ON) Mirrors Bus State(1)

HIGH Standby Mode Disabled (OFF) Disabled (OFF) (Low

Power Bus Monitor is

Active)

High (Unless valid WUP

has been received)

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

9.4.1 CAN Bus States

The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus

state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD terminal. A

recessive bus state is when the bus is biased to VCC / 2 via the high-resistance internal input resistors RIN of the

receiver, corresponding to a logic high on the TXD and RXD terminals.

Figure 9-2. Bus States (Physical Bit Representation)

Figure 9-3. Bias Unit (Recessive Common Mode Bias) and Receiver

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9.4.2 Normal Mode

Select the Normal mode of device operation by setting STB terminal low. The CAN driver and receiver are fully

operational and CAN communication is bi-directional. The driver translates a digital input on TXD to a differential

output on CANH and CANL. The receiver translates the differential signal from CANH and CANL to a digital

output on RXD.

9.4.3 Standby Mode

Activate low power Standby mode by setting STB terminal high. In this mode the bus transmitter will not send

data nor will the normal mode receiver accept data as the bus lines are biased to ground minimizing the system

supply current. Only the low power receiver will be actively monitoring the bus for activity. RXD indicates a valid

wake up event after a wake-up pattern (WUP) has been detected on the Bus. The low power receiver is powered

using only the VIO pin. This allows VCC to be removed reducing power consumption further.

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9.4.3.1 Remote Wake Request via Wake Up Pattern (WUP) in Standby Mode

The TCAN1042 family offers a remote wake request feature that is used to indicate to the host microcontroller

that the bus is active and the node should return to normal operation.

These devices use the multiple filtered dominant wake up pattern (WUP) from the ISO11898-2 (2016) to qualify

bus activity. Once a valid WUP has been received the wake request will be indicated to the microcontroller by a

falling edge and low corresponding to a "filtered" dominant on the RXD output terminal.

The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second

filtered dominant pulse. These filtered dominant, recessive, dominant pulses do not need to occur in immediate

succession. There is no timeout that will occur between filtered bits of the WUP. Once a full WUP has been

detected the device will continue to drive the RXD output low every time an additional filtered dominant signal is

received from the bus.

For a dominant or recessive signal to be considered "filtered", the bus must continually remain in that state for

more than tWK_FILTER. Due to variability in the tWK_FILTER, the following three scenarios can exist:

1. Bus signals that last less than tWK_FILTER(MIN) will never be detected as part of a valid WUP

2. Bus signals that last more than tWK_FILTER(MIN) but less than tWK_FILTER(MAX) may be detected as part of a

valid WUP

3. Bus signals that last more than tWK_FILTER(MAX) will always be detected as part of a valid WUP

Once the first filtered dominant signal is received, the device is now waiting on a filtered recessive signal, other

bus traffic will not reset the bus monitor. Once the filtered recessive signal is received, the monitor is now waiting

on a second filtered dominant signal, and again other bus traffic will not reset the monitor. After reception of the

full WUP, the device will transition to driving the RXD output pin low for the remainder of any dominant signal that

remains on the bus for longer than tWK_FILTER.

Bus VDiff

• tWK_FILTER • tWK_FILTER • tWK_FILTER

Bus

Filtered

Dominant

Filtered

Dominant

Filtered

Recessive

Wake Up Pattern (WUP)

RXD

• tWK_FILTER

Filtered Dominant RXD Output

Bus Wake Via

RXD Requests

Bus Wake via

RXD Request

Waiting for

Filtered

Recessive

Waiting for

Filtered

Dominant

Figure 9-4. Wake Up Pattern (WUP)

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9.4.4 Driver and Receiver Function Tables

Table 9-4. Driver Function Table

DEVICE INPUTS OUTPUTS DRIVEN BUS STATE

STB (1) TXD(1) (2) CANH(1) CANL(1)

All Devices LL H L Dominant

H or Open Z Z Recessive

H or Open X Z Z Recessive

(1) H = high level, L = low level, X = irrelevant, Z = common mode (recessive) bias to VCC / 2. See CAN Bus States for bus state and

common mode bias information.

(2) Devices have an internal pull up to VCC or VIO on TXD terminal. If the TXD terminal is open, the terminal is pulled high and the

transmitter remain in recessive (non-driven) state.

Table 9-5. Receiver Function Table

DEVICE MODE CAN DIFFERENTIAL INPUTS

VID = VCANH – VCANL

BUS STATE RXD TERMINAL(1)

Normal

VID ≥ VIT+(MAX) Dominant L(2)

VIT-(MIN) < VID < VIT+(MAX) ? ?(2)

VID ≤ VIT-(MIN) Recessive H(2)

Open (VID ≈ 0 V) Open H

(1) H = high level, L = low level, ? = indeterminate.

(2) See Receiver Electrical Characteristics section for input thresholds.

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i f i f i f

10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the

data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V

microprocessor applications. The bus termination is shown for illustrative purposes.

10.2 Typical Applications

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 1

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 2

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 3

MCU or DSP

CAN

Controller

CAN

Transceiver

Node n

(with termination)

RTERM

Figure 10-1. Typical CAN Bus Application

10.2.1 Design Requirements

10.2.1.1 Bus Loading, Length and Number of Nodes

The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.

However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a

bus. A large number of nodes requires transceivers with high input impedance such as the TCAN1042 family of

transceivers.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO

11898-2. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus.

Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.

The TCAN1042 family is specified to meet the 1.5 V requirement with a 50Ω load, incorporating the worst case

including parallel transceivers. The differential input resistance of the TCAN1042 family is a minimum of 30 kΩ.

If 100 TCAN1042 family transceivers are in parallel on a bus, this is equivalent to a 300Ω differential load worst

case. That transceiver load of 300 Ω in parallel with the 60Ω gives an equivalent loading of 50 Ω. Therefore,

the TCAN1042 family theoretically supports up to 100 transceivers on a single bus segment. However, for CAN

network design margin must be given for signal loss across the system and cabling, parasitic loadings, network

imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much

lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system

design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to

1 km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

NSTRUMENTS

This flexibility in CAN network design is one of the key strengths of the various extensions and additional

standards that have been built on the original ISO 11898-2 CAN standard. In using this flexibility comes the

responsibility of good network design and balancing these tradeoffs.

10.2.2 Detailed Design Procedures

10.2.2.1 CAN Termination

The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω

characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to

terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes

to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the

cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that

two terminations always exist on the network.

Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node.

If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be

used. (See Figure 10-2). Split termination improves the electromagnetic emissions behavior of the network by

eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.

CAN

Transceiver

CANL

CANH

RTERM/2

CSPLIT

CAN

Transceiver RTERM

RTERM/2

Standard Termination Split Termination

CANL

CANH

Figure 10-2. CAN Bus Termination Concepts

The family of transceivers have variants for both 5-V only applications and applications where level shifting is

needed for a 3.3-V microcontroller.

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TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

Vw 5v Voltage Regulator (e4 TPSxxxx) 5V Volun- Rag u later (0.9. TPSxxu) (w 1'75"“) 3.3V Volllg. I Regulator qu rxo STB TCAN1042 CAN Transcelver RXD A No ‘V' Suﬂ’lx TXD 3.3V MCU ‘ s 2 TC AN I 042 CAN Transceiver WIm Ito Level smmug Wlthoul I/O LBVe‘ Srmng CANH th 'V‘ Sumx Vxn - l 5 2 5 Va GND 1 r l .T.

Figure 10-3. Typical CAN Bus Application Using 5V CAN Controller

Figure 10-4. Typical CAN Bus Application Using 3.3 V CAN Controller

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

TEXAS INSTRUMENTS 5n

10.2.3 Application Curves

VCC (V)

ICC Dominant (mA)

4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

D005

VCC = 4.5 V to 5.5 V VIO = 3.3 V RL = 60 Ω

CL = Open Temp = 25°C STB = 0 V

Figure 10-5. ICC Dominant Current over VCC Supply Voltage

11 Power Supply Recommendations

These devices are designed to operate from a VCC input supply voltage range between 4.5 V and 5.5 V. Some

devices have an output level shifting supply input, VIO, designed for a range between 3 V and 5.5 V. Both supply

inputs must be well regulated. A bulk capacitance, typically 4.7 μF, should be placed near the CAN transceiver's

main VCC supply output, and in addition a bypass capacitor, typically 0.1 μF, should be placed as close to the

device VCC and VIO supply terminals. This helps to reduce supply voltage ripple present on the outputs of the

switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB

power planes and traces.

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TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

I TEXAS INSTRUMENTS

Layout

Robust and reliable bus node design often requires the use of external transient protection device in order to

protect against EFT and surge transients that may occur in industrial environments. Because ESD and transients

have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must

be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of

system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors

should be placed as close to the on-board connectors as possible to prevent noisy transient events from

propagating further into the PCB and system.

12.1 Layout Guidelines

• Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and

noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,

D1, has been used for added protection. The production solution can be either bi-directional TVS diode

or varistor with ratings matching the application requirements. This example also shows optional bus filter

capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the

CANH and CANL lines between the transceiver U1 and connector J1.

• Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device.

• Use supply (VCC) and ground planes to provide low inductance.

Note

High-frequency currents follows the path of least impedance and not the path of least resistance.

• Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to

minimize trace and via inductance.

• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,

examples are C1, C2 on the VCC supply and C6 and C7 on the VIO supply.

• Bus termination: this layout example shows split termination. This is where the termination is split into two

resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split

termination provides common mode filtering for the bus. When bus termination is placed on the board instead

of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the

bus thus also removing the termination. See the application section for information on power ratings needed

for the termination resistor(s).

• To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not

required.

• Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,

this is mandatory to ensure the bit timing into the device is met.

• Terminal 5: For "V" variants of the family, bypass capacitors should be placed as close to the pin as possible

(example C6 and C7). For device options without VIO I/O level shifting, this pin is not internally connected and

can be left floating or tied to any existing net, for example a split pin connection.

• Terminal 8: is shown assuming the mode terminal, STB, will be used. If the device will only be used in normal

mode, R4 is not needed and R5 could be used for the pull down resistor to GND.

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

I TEXAS INSTRUMENTS

12.2 Layout Example

GND

RXD

VCC

TXD

GND

STB

GND

C4 C5

GND

VIO

VCC or VIO R1

Figure 12-1. Layout Example

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TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

l TEXAS INSTRUMENTS Am

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

SLLSES7D – MARCH 2016 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: TCAN1042H TCAN1042HG TCAN1042HGV TCAN1042HV

TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TCAN1042HD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042

TCAN1042HDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042

TCAN1042HGD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042

TCAN1042HGDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042

TCAN1042HGVD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042V

TCAN1042HGVDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042V

TCAN1042HVD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042V

TCAN1042HVDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 1042V

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2021

Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TCAN1042H, TCAN1042HG, TCAN1042HGV, TCAN1042HV :

•Automotive : TCAN1042H-Q1, TCAN1042HG-Q1, TCAN1042HGV-Q1, TCAN1042HV-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component iengtn K0 Dimension designed to accommodate the component Ihlckness 7 W OveraH wtdlh loe Gamer tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TCAN1042HDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TCAN1042HGDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TCAN1042HGVDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TCAN1042HGVDR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1

TCAN1042HVDR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1

TCAN1042HVDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TCAN1042HDR SOIC D 8 2500 853.0 449.0 35.0

TCAN1042HGDR SOIC D 8 2500 853.0 449.0 35.0

TCAN1042HGVDR SOIC D 8 2500 853.0 449.0 35.0

TCAN1042HGVDR SOIC D 8 2500 340.5 336.1 25.0

TCAN1042HVDR SOIC D 8 2500 340.5 336.1 25.0

TCAN1042HVDR SOIC D 8 2500 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

TCAN1042HD D SOIC 8 75 507 8 3940 4.32

TCAN1042HGD D SOIC 8 75 507 8 3940 4.32

TCAN1042HGVD D SOIC 8 75 507 8 3940 4.32

TCAN1042HVD D SOIC 8 75 507 8 3940 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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TCAN1042 Datasheet by Texas Instruments

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