EPC9053 Quick Start Guide Datasheet by EPC

EFFICIENT POWER CONVERSION l
Development Board
EPC9053
Quick Start Guide
EPC2019
Class-E Wireless Power Amplifier
QUICK START GUIDE
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EPC9053
DESCRIPTION
The EPC9053 is a high efficiency, differential mode Class-E amplifier
development board that can operate up to 15 MHz. Higher frequency
may be possible but is currently under evaluation. The purpose of this
development board is to simplify the evaluation process of class-E
amplifier technology using eGaN® FETs by allowing engineers to easily
mount all the critical class-E components on a single board that can be
easily connected into an existing system.
This board may also be used for applications where a low side switch is
utilized. Examples include, and are not limited to, push-pull converters,
current-mode Class D amplifiers, common source bi-directional switch,
and generic high voltage narrow pulse width applications such as LiDAR.
The amplifier board features the 200 V rated EPC2019 eGaN FET. The
amplifier is set to operate in differential mode and can be re-configured to
operate in single-ended mode and includes the gate driver and logic
supply regulator.
For more information on the EPC2019 eGaN FETs please refer to the
datasheet available from EPC at www.epc-co.com. The datasheet should
be read in conjunction with this quick start guide.
DETAILED DESCRIPTION
The Amplifier Board (EPC9053)
Figure 1 shows the schematic of a single-ended, Class-E amplifier
with ideal operation waveforms where the amplifier is connected to a
tuned load such as a highly resonant wireless power coil. The amplifier
has not been configure due to the specific design requirements such as
load resistance and operating frequency. The design equations of the
specific Class-E amplifier support components are given in this guide
and specific values suitable for a RF amplifier application can then be
calculated.
Figure 2 shows the differential mode Class-E amplifier EPC9053 demo board
power circuit schematic. In this mode the output is connected between Out
1 and Out 2. A block-wave external oscillator with 50 % duty cycle and 0 V – 5
V signal amplitude is used as a signal for the board. Duty cycle modulation
is recommended only for advanced users who are familiar with the Class-E
amplifier operation and require additional efficiency.
The EPC9053 is also provided with a 5 V regulator to supply power to the logic
circutis and gate driver on board such as the gate driver. Adding a 0 Ω resistor
in position R90 allows the EPC9053 to be powered using a single-supply
voltage; however in this configuration the maximum operating voltage is
limited to between 7 V and 12 V.
Single-ended Mode operation
Although the default configuration is differential mode, the demo board
can be re-configured for single-ended operation by shorting out
C74 (which disables only the drive circuits) and connecting the
load between Out 1 and GND only (see figures 2 and 5 for details).
Class-E amplifier operating limitations
The impact of load resistance variation is significant to the performance of
the Class-E amplifier, and must be carefully analyzed to select the optimal
design resistance.
The impact of load resistance (RLoad – Real part of ZLoad) variation on the
operation of the Class-E amplifier is shown in figure 3. When operating a
Class-E amplifier with a load resistance (RLoad – Real part of ZLoad) that
is below the design value (see the waveform on the left of figure
3), the load tends to draw current from the amplifier too quickly.
To compensate for this condition, the amplifier supply voltage is
increased to yield the required output power. The shorter duration
of the energy charge cycle leads to a significant increase in the
voltage to which the switching device is exposed. This is done in
order to capture sufficient energy and results in device body diode
conduction during the remainder of the device off period. This
period is characterized by a linear increase in device losses as a
function of decreasing load resistance (RLoad).
When operating the Class-E amplifier with a load resistance (RLoad) that is
above the design value (see the waveform on the right of figure 3), the
load tends to draw insufficient current from the amplifier, resulting in an
incomplete voltage transition. When the device switches there is a
residual voltage across the device, which leads to shunt capacitance
(COSS + Csh) losses. This period in the cycle is characterized by an expo-
nential increase in device losses as function of increasing reflected load
resistance.
* Maximum current depends on die temperature – actual maximum current will be subject to switching
frequency, bus voltage and thermals.
EPC9053 amplifier board photo
Table 1: Performance Summary (TA = 25°C) EPC9053
Symbol Parameter Conditions Min Max Units
VIN
Main Supply Voltage
Range
Class-E Configuration 0 40 V
Current Mode Class-D
Configuration 0 60 V
Push-Pull Configuration 0 80 V
VDD
Control Supply Input
Range 7 12 V
IOUT
Switch Node Output
Current (each) 1* A
VOSC
Oscillator Input
Threshold Input ‘Low’ -0.3 1.5 V
Input ‘High’ 3.5 5 V
Given these two extremes of the operating load resistance (RM), the load 3 This specifically designed; 1) the extra inductor (L1), 2] the shunt capacitor (Cm) and, 3) the less by within the frequency capability of this development board. The design needs to have a specific load resistance (RM) value and desired load power (PM that is used to begin the design, which then drives the values of the other impedance value (Ztml shown in figure 1.The reactive component of Zmad supply the external by 0530 C Finally,the choke lel can be designed using equation 5 and, in this case, current, which can lead to a more stable operating amplifier. A toorlow value Will lead to increased operating lossesand changethe mode ofoperation olthe
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EPC9053
Given these two extremes of the operating load resistance (RLoad), the
optimal point between them must be determined. In this case, the
optimal point yields the same device losses for each of the extreme load
resistance points and is shown in the lower center graph of figure 3. This
optimal design point can be found through trial and error, or using circuit
simulation.
Class-E amplifier design
For this amplifier only three components need to be specifically
designed; 1) the extra inductor (Le), 2) the shunt capacitor (Csh) and, 3) the
selection of a suitable switching device. The RF choke (LRFck) value is less
critical and hence can be chosen or designed.
The design equations for the Class-E amplifier have been derived by
N. Sokal [1]. To simplify these equations, the value of QL in [1] is set to in-
finity, which is a reasonable approximation in most applications within
the frequency capability of this development board. The design needs to
have a specific load resistance (RLoad) value and desired load power (PLoad)
that is used to begin the design, which then drives the values of the other
components, including the magnitude of the supply voltage.
The Class-E amplifier passive component design starts with the load
impedance value (ZLoad) shown in figure 1. The reactive component of ZLoad
is tuned out using a series capacitor CS, which also serves as a DC block,
resulting in RLoad. It is a common mistake to ignore the need for the DC
block, where a failure to do so can yield a DC current from the supply
through to the load, and lead to additional losses in several components
in that path.
First, using the equations in figure 4, both the extra inductor
Le (equation 2 and shunt capacitor (equation 3) values can be
determined [2], [3]. The value of the shunt capacitor includes the
COSS of the switching device, which must be subtracted from the
calculated value to yield the actual external capacitor (Csh) value. To
do this, first the magnitude of the supply voltage (VDD) is calculated
using equation 1, which in turn can be used to determine the peak
device voltage (3.56·VDD).
The RMS value of the peak device voltage is then used to determine the
COSSQ of the device at that voltage. This is the capacitance that will be
deducted from the calculated shunt capacitor to reveal the external
shunt capacitor (Csh) value. The COSSQ of the device can be calculated by
integrating the COSS as function of voltage using equation 4. If the COSSQ
value is larger than the calculated shunt capacitance, then the design
cannot be realized for the load resistance specified and a new load
resistance (RLoad) must be chosen.
Finally, the choke (LRFck) can be designed using equation 5 and, in this case,
a minimum value is specified. Larger values yield lower ripple current,
which can lead to a more stable operating amplifier. A too-low value will
lead to increased operating losses and change the mode of operation of the
amplifier. In some cases this can be intentional.
Here:
RLoad = Load Resistance [Ω]
PLoad = Load Power [W]
VDD = Amplifier Supply Voltage [V]
f = Operating Frequency [Hz]
Le = Extra Inductor [H]
Csh = Shunt Capacitor [F]
COSS = Output Capacitance of the FET [F]
COSSQ = Charge Equivalent Device Output Capacitance [F].
VDS = Drain-Source Voltage of the FET [V]
LRFck = RF Choke Inductor [H]
CS = Series Tuning Capacitor [F]
ZLoad = Load Impedance [Ω]
NOTE. that in the case of a differential mode amplifier the calculated value
of Le is shared between each of the circuits and thus must be divided by
two for each physical component on the board.
[1] N.O. Sokal, “Class-E RF Power Amplifiers,” QEX, Issue 204, pp. 9–20,
January/ February 2001.
[2] M. Kazimierczuk, “Collector amplitude modulation of the Class-E
tuned power amplifier,” IEEE Transactions on Circuits and Systems,
June 1984, Vol.31, No. 6, pp. 543–549.
[3] Z. Xu, H. Lv, Y. Zhang, Y. Zhang, “Analysis and Design of Class-E Power
Amplifier employing SiC MESFETs,“ IEEE International Conference on
Electron Devices and Solid-State Circuits (EDSSC) 2009, 25–27
December 2009, pp 28–31.
QUICK START PROCEDURE
The EPC9053 amplifier board is easy to set up to evaluate the
performance of the eGaN FET in a class-E amplifier application. Once
the design of the passive components has been completed and
installed, then the board can be powered up and tested.
1. Make sure the entire system is fully assembled prior to making
electrical connections including an applicable load.
2. With power off, connect the main input power supply bus to J62
as shown in figure 5. Note the polarity of the supply connector.
Set the voltage to 0 V.
3. With power off, connect the logic input power supply bus to J90
as shown in figure 5. Note the polarity of the supply connector.
Set the voltage to between 7 V and 12 V.
4. Make sure all instrumentation is connected to the system.
This includes the external oscillator to control the circuit.
5. Turn on the logic supply voltage.
6. Turn on the main supply voltage and increase to the desired
value. Note operating conditions and in particular the thermal
performance and voltage of the FETs to prevent
over-temperature and over-voltage failure.
7. Once operation has been confirmed, observe the device voltage,
efficiency and other parameters on both the amplifier and
device boards.
8. For shutdown, please follow steps in the reverse order.
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EPC9053
NOTE. When measuring the high frequency content switch-node, care must be taken
to avoid long ground leads. An oscilloscope probe connection (preferred method) has
been built into the board to simplify the measurement of the Drain-Source Voltage
(shown in figure 5). The choice of oscilloscope probe needs to consider tip capacitance
where this will appear in parallel with the shunt capacitance thereby altering the operating
point of the amplifier.
Pre-Cautions
The EPC9053 development board showcases the EPC2019 eGaN FETs in
a class-E amplifier application. Although the electrical performance
surpasses that of traditional silicon devices, their relatively smaller size
does require attention paid to thermal management techniques.
Figure 3: Class-E operation under various load conditions that can be used to determine the optimal design load resistance (Rload).
Figure 2: EPC9053 power circuit schematic.
Figure 1: Single-ended, Class-E amplifier with ideal operation waveforms.
+
Le1x Le2x
L10 L20
Q1 Q2
CCQ1 CCQ2
Coil
Connection
J62
VIN
GND-
Single-ended
operation
VDD
LRFck Le
Csh
CS
ZLoad
Q1
VDS
ID
50% Time
V / I
Ideal Waveforms
VDS ID
3.56 x VDD
IDID
V / IV / I
PFETloss
RLoad
RLoad_Design
V / I
VDS VDS ID
VDS
50%
50%
50%
Time TimeTime
RLoad < Design Point
RLoad = Design Point
RLoad > Design Point
Body Diode
Conduction
Capacitance
(C
OSS
+ C
sh
)
Losses
~6.5 x VDD ~2 x VDD
Optimal Design
3.56 x VDD
Drives FET Voltage Rating Drives FET COSS Choice
The EPC9053 development board has no current or thermal protection
and care must be exercised not to over-current or over-temperature
the devices. Excessively wide load impedance range variations can lead
to increased losses in the devices. The operator must observe the
temperature of the gate driver and eGaN FETs to ensure that both are
operating within the thermal limits as per the datasheets. Always check
operating conditions and monitor the temperature of the EPC devices
using an IR camera.
,(1 +4) .P L Vi, u» Am lifier Board — Front-side
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EPC9053
Figure 4: Class-E amplifier design process with equations.
Figure 5: Proper connection and measurement setup for the amplifier board.
VIN Supply
(Note Polarity)
Output 1 Pad
Extra Inductor 1
Shunt Capacitor 1
Shunt Capacitor 2
Extra Inductor 2
External
Oscillator
Out A Oscilloscope Probe
Ground Post
Single Supply
Jumper
RF Choke 2
+
+
7 V - 12 VDC 0 V - 40 VDCmax
VLogic Supply
(Note Polarity)
Out B Oscilloscope Probe
Ground Pad Output
Output 2 Pad
RF Choke 1
32 π f
V
DD
LRFck
Le
Csh
CS
ZLoad
Q1
Capacitance
Voltage
COSSQ
COSS
COSSQ = COSS (VDS) dvDS
1
VDD
VDD
0
15
2
3
4
4
7
6
DC Block
RLoad
COSSQ + Csh =
RLoad PLoad (π2 + 4)
RLoad
1
2
3
4
8
(π2 + 4)
4 f
RLoad
π (π2 4)
f RLoad
π2 (π2 + 4)
VDD =
LRFck
Le =
>
4
5
6
7
Do not use probe gm lead Place probe tip in large via
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EPC9053
Figure 6: Proper measurement of the drain voltage using the hole and ground post.
Table 2: Bill of Materials - Amplifier Board
Item Qty Reference Part Description Manufacturer Part #
1 2 C1, C2 22 pF, 50 V Würth 885012005057
2 2 C10, C20 2.2 µF 100 V Taiyo Yuden HMK325B7225KN-T
3 1 C40 4.7 µF, 10 V Samsung CL05A475MP5NRNC
4 3 C41, C70, C71 100 nF, 16 V Würth 885012205037
5 2 C73, C74 22 pF, 50 V Würth 885012005057
6 3 C90, C91, C92 1 µF, 25 V Würth 885012206076
7 2 CQ1, CQ2 TBD TBD TBD
8 2 D70, D71 DNP (40 V 30 mA) Diodes Inc. SDM03U40
9 1 GP1 .1" Male Vert. Würth 61300111121
10 1 J62 .156" Male Vert. Würth 645002114822
11 2 J70, J90 .1" Male Vert. Würth 61300211121
12 2 L10, L20 TBD TBD TBD
13 2 L11, L21 TBD TBD TBD
14 2 Le11, Le21 TBD TBD TBD
15 2 Le12, Le22 TBD TBD TBD
16 2 Q1, Q2 200 V, 8.5 A, 50 mΩ EPC EPC2019
17 2 R11, R21 2.2 Ω Yageo RC0402JR-072R2L
18 2 R70, R71 0 Ω Samsung RC1005J000CS
19 1 R73 10k Yageo RC0402FR-0710KL
20 1 R74 10k
Panasonic ERJ-2GEJ103X
21 1 R90 DNP (0 Ω)
Stackpole RMCF0603ZT0R00
22 1 U40 100 V eGaN Driver Texas Instruments
LM5113TM
23 1 U70 2 In NAND
Fairchild NC7SZ00L6X
24 1 U71 2 In AND
Fairchild NC7SZ08L6X
25 1 U90 5.0 V, 250 mA, DFN
Microchip MCP1703T-5002E/MC
EPC would like to acknowledge Würth Electronics (www.we-online.com/web/en/wuerth_elektronik/start.php) for their support of this project.
Do not use
probe ground
lead
Ground
probe
against
post
Place probe tip
in large via Minimize
loop
H—D >—4> aw g: g aw g 4%
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EPC9053
7.5 VDC – 12 VDC
Logic Supply Regulator
V7IN
V7IN
V7IN
Main Supply
2.2 Ω
1 2
R11
2.2 Ω
1 2
R21
GRH
GRL
5V
5 V
5 V
5 V
GLH
GLL
Gate Driver
U40
LM5113TM
L_Sig
R_Sig
LO GIC
SDM03U40
40 V, 30 mA
D71
5V
5 V
5 V
Deadtime Left
Deadtime Right
Oscillator In put
A
B
U70
NC7SZ00L6X
5 V
OSC GRH GRL
GLLGLH
TBD
L10
TBD
L20
OSC
OSC
OSC
Logic Supply
VSUP
VSUP
VSUP
VSUP VSUP
VSUP
TBD
CQ2
TBD
CQ1
OUTA OUT1
OUT2
OUTB
Q1
EPC2019
200 V, 8.5 A, 50 mΩ
Q2
EPC2019
2.2 µF, 100 V
200 V, 8.5 A, 50 mΩ
C20
2.2 µF, 100 V
C10 TBD
Le11
TBD
Le12
TBD
Le21
TBD
Le22
TBD
L11
TBD
L21
SDM03U40
40 V, 30 mA
D70
A
B
Y
U71
NC7SZ08L6X
22 pF, 50 V
22 pF, 50 V
C1
OPEN
1 2
R90
GND
.1" Male Vert.
1
2
J90
5 V
1 µF, 25 V 1 µF, 25 V 1 µF, 25 V
C90
MCP1703T-5002E/MC
OUT
GND
IN
GND
U90
nSD
nSD
5 V
10k
1
2
R74
.1" Male Vert.
1
2
J70
4.7 µF, 10 V
C40
0 Ω
1 2
R70
0 Ω
1 2
R71
100 nF, 16 V
C70
10k
12
R73 1
.1" Male Vert.
GP1
Ground Post
1
ProbeHole
ProbeHole
PH1
1
PH2
1
2
.156" Male Vert.
J62
FD1
Local Fiducials
FD2 FD3
100 nF, 16 V
C71
100 nF, 16 V
C41
22 pF, 50 V
C2
C73
22 pF, 50 V
C74
C91 C92
5.0 V, 250 mA, DFN
Figure 7: EPC9053 Class-E amplifier schematic.
EFFIEIENT POWER (ONVERSION l
Demonstration Board Notification
The EPC9053 boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European
Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain
components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
EPC Products are distributed through Digi-Key.
www.digikey.com
For More Information:
Please contact info@epc-co.com
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