CSD17484F4 Datasheet by Texas Instruments

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CSD17484F4 30-V N-Channel FemtoFET™ MOSFET
1 Features
• Low on-resistance
• Ultra-low Qg and Qgd
• Low-threshold voltage
• Ultra-small footprint (0402 Case Size)
– 1.0 mm × 0.6 mm
• Ultra-low profile
– 0.2-mm height
• Integrated ESD protection diode
– Rated > 4-kV HBM
– Rated > 2-kV CDM
• Lead and halogen free
• RoHS compliant
2 Applications
• Optimized for load switch applications
• Optimized for general purpose switching
applications
• Battery applications
• Handheld and mobile applications
3 Description
This 99-mΩ, 30-V, N-Channel FemtoFET™ MOSFET
is designed and optimized to minimize the footprint
in many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
0.60 mm
1.00 mm
0.20 mm
Figure 3-1. Typical Part Dimensions
Product Summary
TA = 25°C TYPICAL VALUE UNIT
VDS Drain-to-Source Voltage 30 V
QgGate Charge Total (4.5 V) 920 pC
Qgd Gate Charge Gate-to-Drain 75 pC
RDS(on) Drain-to-Source On-Resistance
VGS = 1.8 V 170
mΩ
VGS = 2.5 V 125
VGS = 4.5 V 107
VGS = 8.0 V 99
VGS(th) Threshold Voltage 0.85 V
Device Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
CSD17484F4 3000
7-Inch Reel
Femto (0402)
1.00-mm × 0.60-mm
Land Grid Array (LGA)
Tape
and
Reel
CSD17484F4T 250
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C VALUE UNIT
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage 12 V
IDContinuous Drain Current(1) 3.0 A
IDM Pulsed Drain Current(1) (2) 18 A
IG
Continuous Gate Clamp Current 35 mA
Pulsed Gate Clamp Current(2) 350
PDPower Dissipation 500 mW
V(ESD)
Human-Body Model (HBM) 4 kV
Charged-Device Model (CDM) 2
TJ,
Tstg
Operating Junction,
Storage Temperature –55 to 150 °C
EAS
Avalanche Energy, Single Pulse ID = 7.1 A,
L = 0.1 mH, RG = 25 Ω 2.5 mJ
(1) Typical RθJA = 85°C/W on 1-in2 (6.45-cm2), 2-oz
(0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4
PCB.
(2) Pulse duration ≤ 100 μs, duty cycle ≤ 1%.
D
G S
Figure 3-2. Top View
CSD17484F4
SLPS550D – MAY 2015 – REVISED FEBRUARY 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................ 4
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Trademarks................................................................. 7
7 Mechanical, Packaging, and Orderable Information.... 8
7.1 Mechanical Dimensions.............................................. 8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
4 Revision History
Changes from Revision C (December 2019) to Revision D (February 2022) Page
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision B (September 2017) to Revision C (December 2019) Page
• Changed On-State Resistance vs Gate-to-Source Voltage by truncating VGS from 20 V to 12 V......................4
Changes from Revision A (August 2017) to Revision B (September 2017) Page
• Deleted the CSD68830F4 Embossed Carrier Tape Dimensions section............................................................9
Changes from Revision * (May 2015) to Revision A (August 2017) Page
• Added the Section 6.1 and the Section 6 sections ............................................................................................ 7
• Updated the Section 7 section............................................................................................................................8
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 100 nA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 12 V 50 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 0.65 0.85 1.10 V
RDS(on) Drain-to-source on-resistance
VGS = 1.8 V, IDS = 0.5 A 170 270
mΩ
VGS = 2.5 V, IDS = 0.5 A 125 160
VGS = 4.5 V, IDS = 0.5 A 107 128
VGS = 8 V, IDS = 0.5 A 99 121
gfs Transconductance VDS = 15 V, IDS = 0.5 A 4 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
150 195 pF
Coss Output capacitance 44 57 pF
Crss Reverse transfer capacitance 2.2 2.9 pF
RGSeries gate resistance 8 Ω
QgGate charge total (4.5 V)
VDS = 15 V, IDS = 0.5 A
920 1200 pC
QgGate charge total (8.0 V) 1570 2040 pC
Qgd Gate charge gate-to-drain 75 pC
Qgs Gate charge gate-to-source 280 pC
Qg(th) Gate charge at Vth 140 pC
Qoss Output charge VDS = 15 V, VGS = 0 V 1400 pC
td(on) Turnon delay time
VDS = 15 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 2 Ω
3 ns
trRise time 1 ns
td(off) Turnoff delay time 11 ns
tfFall time 4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 0.5 A, VGS = 0 V 0.73 0.9 V
Qrr Reverse recovery charge VDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs 1300 pC
trr Reverse recovery time 6.2 ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC TYPICAL VALUES UNIT
RθJA
Junction-to-ambient thermal resistance(1) 85 °C/W
Junction-to-ambient thermal resistance(2) 245
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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I TEXAS INSTRUMENTS 2m A Narmallzed Thermal lmpedance lo — 50% 10% 2% Slrlgla Pulse — 30% 5% 1% I 01 0.01 mm”: fiafilcrw TFP’ iw' M 0 001 lE~5 0.00m 00m 001 BI 10 loo 1000 ln- Pulse Durallon lsl
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
VDS - Drain-to-Source Voltage (V)
IDS - Drain-to-Source Current (A)
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
0
1
2
3
4
5
6
7
8
9
10
D002
VGS = 1.8 V
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
Figure 5-1. Saturation Characteristics
VGS - Gate-to-Source Voltage (V)
IDS - Drain-to-Source Current (A)
0 0.5 1 1.5 2 2.5 3 3.5 4
0
1
2
3
4
5
6
7
8
9
10
D003
TC = 125°C
TC = 25°C
TC = -55°C
VDS = 5 V
Figure 5-2. Transfer Characteristics
Figure 5-3. Transient Thermal Impedance
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TEXAS INSTRUMENTS 1000 2w
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
0
1
2
3
4
5
6
7
8
D004
ID = 0.5 A VDS = 15 V
Figure 5-4. Gate Charge
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
0 3 6 9 12 15 18 21 24 27 30
1
10
100
1000
D005
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Figure 5-5. Capacitance
TC - Case Temperature (°C)
VGS(th) - Threshold Voltage (V)
-75 -50 -25 0 25 50 75 100 125 150 175
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
D006
ID = 250 µA
Figure 5-6. Threshold Voltage vs Temperature
Figure 5-7. On-State Resistance vs Gate-to-Source
Voltage
TC - Case Temperature (qC)
Normalized On-State Resistance
-75 -50 -25 0 25 50 75 100 125 150 175
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
D008
VGS = 2.5 V
VGS = 4.5 V
ID = 0.5 A
Figure 5-8. Normalized On-State Resistance vs
Temperature
VSD - Source-To-Drain Voltage (V)
ISD - Source-To-Drain Current (A)
0 0.2 0.4 0.6 0.8 1
0.0001
0.001
0.01
0.1
1
10
D009
TC = 25qC
TC = 125qC
Figure 5-9. Typical Diode Forward Voltage
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TEXAS INSTRUMENTS mo mu 35
VDS - Drain-To-Source Voltage (V)
IDS - Drain-To-Source Current (A)
0.01 0.1 1 10 50
0.01
0.1
1
10
100
D010
100 ms
10 ms
1 ms
100 µs
10 µs
Single pulse, typical RθJA = 85°C/W
Figure 5-10. Maximum Safe Operating Area
TAV - Time in Avalanche (ms)
IAV - Peak Avalanche Current (A)
0.001 0.01 0.1 1
0.1
1
10
100
D011
TC = 25q C
TC = 125q C
Figure 5-11. Single Pulse Unclamped Inductive
Switching
TA - Ambient Temperature (°C)
IDS - Drain-to-Source Current (A)
-50 -25 0 25 50 75 100 125 150 175
0
0.5
1
1.5
2
2.5
3
3.5
D012
Figure 5-12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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CSD17484F4
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TEXAS INSTRUMENTS 1114 E! 1 0.96 PM I INDEXAREA \\\\\\\\\\ o s \\ i NW \\\\\\\ \w‘ W \ \me \\ \ .7 ii 2—4'La J SEATING PLANE \ \\ \\ \\\\\\\\\\ q xxx; mu\;\\>\\§ Maui 2 o 55
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a PB-free solder land design.
Table 7-1. Pin
Configuration
POSITION DESIGNATION
Pin 1 Gate
Pin 2 Source
Pin 3 Drain
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{5‘ TEXAS INSTRUMENTS
7.2 Recommended Minimum PCB Layout
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EXAMPLE BOARD LAYOUT
2X (0.25)
2X (0.15) 0.05 MIN
ALL AROUND
(0.65)
(0.35)
(0.25)
(0.5)
(R ) TYP0.05
4220651/B 08/2015
PicoStar - 0.35 mm max heightYJC0003A
PicoStar
PKG
1
2
SYMM
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
3
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
TM
TM
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
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EXAMPLE STENCIL DESIGN
2X (0.15)
2X (0.25)
2X (0.2)
(0.65)
(0.25)
(0.5)
(0.4)
(R ) TYP0.05
4220651/B 08/2015
PicoStar - 0.35 mm max heightYJC0003A
PicoStar
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
TM
TM
SOLDER PASTE EXAMPLE
ON 0.075 - 0.1 mm THICK STENCIL
SCALE:50X
PKG
1
2
SYMM
3
2X SOLDER MASK EDGE
A. All dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD17484F4 ACTIVE PICOSTAR YJJ 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 G2
CSD17484F4T ACTIVE PICOSTAR YJJ 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 G2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD17484F4 PICOST
AR YJJ 3 3000 178.0 9.2 0.7 1.1 0.28 4.0 8.0 Q2
CSD17484F4T PICOST
AR YJJ 3 250 178.0 9.2 0.7 1.1 0.28 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD17484F4 PICOSTAR YJJ 3 3000 220.0 220.0 35.0
CSD17484F4T PICOSTAR YJJ 3 250 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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