TPS62090-Q1 Datasheet by Texas Instruments

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TPS62090-Q1 3-A High-Efficiency Synchronous Step-Down Converter
With DCS-Control™
1 Features
Qualified for automotive applications
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
junction operating temperature range
Device HBM ESD classification level H2
Device CDM ESD classification level C6
2.5-V to 6-V input voltage range
• DCS-Control
95% converter efficiency
Power save mode
20-µA operating quiescent current
100% duty cycle for lowest dropout
2.8-MHz and 1.4-MHz typical switching frequency
0.8-V to VIN adjustable output voltage
Output discharge function
Adjustable soft start
Hiccup short-circuit protection
Output voltage tracking
Wide output capacitance selection
Available in 3-mm × 3-mm 16-pin QFN package
New product available: TPS62813-Q1, 6-V step-
down converter in 2-mm × 3-mm QFN package
with wettable flanks
2 Applications
Automotive applications
Distributed power supplies
Processor supply
Battery-powered applications
3 Description
The TPS62090Q devices are a family of high-
frequency, synchronous, step-down converters
optimized for small solution size, high efficiency,
and are suitable for battery-powered applications.
To maximize efficiency, the converters operate in
pulse width modulation (PWM) mode with a nominal
switching frequency of 2.8 MHz to 1.4 MHz and
automatically enter power save mode operation at
light load currents. When used in distributed power
supplies and point-of-load regulation, the devices
allow voltage tracking to other voltage rails and
tolerate output capacitors ranging from 10 µF up
to 150 µF and beyond. Using the DCS-Control
topology, the devices achieve excellent load transient
performance and accurate output voltage regulation.
The output voltage start-up ramp is controlled by
the SS pin, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
enable and power good pins. In power save mode,
the devices operate at typically 20-µA quiescent
current. Power save mode is entered automatically
and seamlessly maintaining high efficiency over the
entire load current range.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS62090Q QFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
R1
200 k
R2
160 k
C2
22 µF
R3
500 k
C1
10 µF
VIN
2.5 V to 6 V
VPG
VOUT
1.8 V / 3.0 A
L1
470 nH
TPS62090Q
C3
10 nF
C4
10 nF
VOUT
SS
PVIN
PVIN
AVIN
EN
CP
CN
AGND
SW
SW
VOS
FB
PG
FREQ
PGND PGND
Copyright © 2016, Texas Instruments Incorporated
Typical Application
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
G004
Efficiency
TPS62090-Q1
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
8.3 System Examples..................................................... 19
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 Receiving Notification of Documentation Updates.. 23
11.4 Support Resources................................................. 23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution.............................. 23
11.7 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2016) to Revision C (November 2021) Page
Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
Added link to the TPS62813-Q1.........................................................................................................................1
Changes from Revision A (August 2013) to Revision B (December 2016) Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section................................................................................................................................................................ 1
Added CN and CP pin voltage............................................................................................................................4
Added typical value of VH and VL ...................................................................................................................... 5
Added new graphs to the Typical Characteristics section ..................................................................................6
Added Switching frequency curves for VOUT = 1 V and VOUT = 3.3 V............................................................ 6
Added Enable and Disable (EN) section............................................................................................................ 9
Added Hiccup current limit during startup ..........................................................................................................9
Added Charge Pump (CP, CN) section.............................................................................................................11
Updated Input and Output Capacitor Selection section....................................................................................16
Moved graphs from Typical Characteristics to Application Curves section ......................................................17
Updated TPS62090Q Layout............................................................................................................................22
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5 Pin Configuration and Functions
1516
Exposed
Thermal Pad*
VOS
PGND
1
2
SW
SW
3
4
FREQ
PG
1314
PGND
EN
6
57 8
12
11
10
9
FB
AGND
CP
CN
PVIN
AVIN
SS
PVIN
The exposed thermal pad is connected to AGND.
Figure 5-1. RGT Package 16-Pin QFN With Exposed Thermal Pad Top View
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage(2)
PVIN, AVIN, FB, SS, EN, FREQ, VOS –0.3 7
VSW, PG –0.3 VIN + 0.3
CN, CP -0.3 VIN + 7
Power Good sink current, PG 1 mA
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
For additional information, see Section 8.1.
MIN MAX UNIT
VIN Input voltage 2.5 6 V
TJOperating junction temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)
TPS62090-Q1
UNITRGT (QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 45.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.9 °C/W
RθJB Junction-to-board thermal resistance 19 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 19 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VIN = 3.6 V, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 2.5 6 V
IQIN Quiescent current Not switching, FB = FB +5 %, Into PVIN and AVIN 20 µA
Isd Shutdown current Into PVIN and AVIN 0.6 5 µA
UVLO Undervoltage lockout threshold VIN falling 2.1 2.2 2.3 V
Undervoltage lockout hysteresis 200 mV
Thermal shutdown Temperature rising 150 °C
Thermal shutdown hysteresis 20 °C
CONTROL SIGNALS EN, FREQ
VHHigh level input voltage VIN = 2.5 to 6 V 1 0.65 V
VLLow level input voltage VIN = 2.5 to 6 V 0.6 0.4 V
Ilkg Input leakage current EN, FREQ = GND or VIN 10 100 nA
RPD Pulldown resistance 400
SOFT START
ISS Soft-start current 6.3 7.5 8.7 µA
POWER GOOD
Vth Power good threshold Output voltage rising 95%
Output voltage falling 90%
VLLow level voltage I(sink) = 1 mA 0.4 V
IPG PG sinking current 1 mA
Ilkg Leakage current VPG = 3.6 V 10 200 nA
POWER SWITCH
RDS(on
)
High-side FET on-resistance ISW = 500 mA 50
Low-side FET on-resistance ISW = 500 mA 40
ILIM High-side FET switch current limit 3.7 4.6 5.5 A
fsSwitching frequency FREQ = GND, IOUT = 3 A 2.8 MHz
FREQ = VIN, IOUT = 3 A 1.4 MHz
OUTPUT
VsOutput voltage 0.8 VIN V
Rod Output discharge resistor EN = GND, VOUT = 1.8 V 200 Ω
VFB Feedback regulation voltage 0.8 V
VFB Feedback voltage
accuracy(1) (2) VIN ≥ VOUT + 1 V
IOUT = 1 A, PWM mode –1.4% 1.4%
IOUT = 0 mA, FREQ = 2.8 MHz, VOUT
≥ 0.8 V, PFM mode –1.4% 3%
IOUT = 0 mA, FREQ = 1.4 MHz, VOUT
≥ 1.2 V, PFM mode –1.4% 3%
IOUT = 0 mA, FREQ = 1.4 MHz, VOUT
< 1.2 V, PFM mode –1.4% 3.7%
IFB Feedback input bias current VFB = 0.8 V 10 100 nA
VOUT Output voltage accuracy(2)
VIN ≥ VOUT + 1 V, fixed output
voltage, f = 2.8 MHz, L = 0.47
µH, COUT = 22 µF or f = 1.4
MHz, L = 1 µH, COUT = 22 µF
IOUT = 1 A, PWM mode –1.4% 1.4%
IOUT = 0 mA, FREQ = high and low,
PFM mode –1.4% 2.5%
Line regulation VOUT = 1.8 V, PWM operation 0.016% V
Load regulation VOUT = 1.8 V, PWM operation 0.04% A
(1) For output voltages < 1.2 V, use a 2 × 22 µF output capacitance to achieve 3% output voltage accuracy.
(2) For more information, see Section 7.4.2.
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TEXAS INSTRUMENTS 2mm auou 3mm 2mm
6.6 Typical Characteristics
0
10
20
30
40
50
60
70
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
Resistance ()
TA = 85°C
TA = 25°C
TA = −40°C
G024
Figure 6-1. High-Side FET ON-Resistance vs Input
Voltage
0
5
10
15
20
25
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Voltage (V)
Current (µA)
TA = 85 °C
TA = 25 °C
TA = −40 °C
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
G011
Figure 6-2. Quiescent Current vs Input Voltage
Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
D030
VIN = 2.8 V
VIN = 3.3 V
VIN = 5.0 V
VOUT = 1 V L = 1 µH FREQ = High
Figure 6-3. Switching Frequency vs Load Current
Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
2500
3000
D031
VIN = 2.8 V
VIN = 3.3 V
VIN = 5.0 V
VOUT = 1 V L = 0.4 µH FREQ = Low
Figure 6-4. Switching Frequency vs Load Current
Input Voltage (V)
Switching Frequency (kHz)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
500
1000
1500
2000
2500
3000
D032
/ +)5(4 /RZ
/ +)5(4 +LJK
VOUT = 1 V IOUT = 1 A
Figure 6-5. Frequency vs Input Voltage
Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
D033
VIN = 2.8 V
VIN = 3.3 V
VIN = 5.0 V
VOUT = 1.8 V L = 1 µH FREQ = High
Figure 6-6. Frequency vs Load Current
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Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
2500
3000
D034
VIN = 2.8 V
VIN = 3.3 V
VIN = 5.0 V
VOUT = 1.8 V L = 0.4 µH FREQ = Low
Figure 6-7. Frequency vs Load Current
Input Voltage (V)
Switching Frequency (kHz)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
500
1000
1500
2000
2500
3000
D035
/ +)5(4 /RZ
/ +)5(4 +LJK
VOUT = 1.8 V IOUT = 1 A
Figure 6-8. Frequency vs Input Voltage
Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
D036
VIN = 5.0 V
VOUT = 3.3 V L = 1 µH FREQ = High
Figure 6-9. Frequency vs Load Current
Load (A)
Switching Frequency (kHz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
500
1000
1500
2000
2500
3000
D037
VIN = 5.0 V
VOUT = 3.3 V L = 0.4 µH FREQ = Low
Figure 6-10. Frequency vs Load Current
Input Voltage (V)
Switching Frequency (kHz)
3.5 4.0 4.5 5.0 5.5 6.0
0
500
1000
1500
2000
2500
3000
3500
D038
/ +)5(4 /RZ
/ +)5(4 +LJK
VOUT = 3.3 V IOUT = 1 A
Figure 6-11. Frequency vs Input Voltage
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7 Detailed Description
7.1 Overview
The TPS62090Q synchronous switched mode converter is based on DCS-Control (Direct Control with
Seamless transition into power save mode). DCS-Control is an advanced regulation topology that combines
the advantages of hysteretic and voltage mode control.
The DCS-Control topology operates in Pulse Width Modulation (PWM) mode for medium to heavy load
conditions and in power save mode at light load currents. In PWM, the converter operates with nominal switching
frequency of 2.8 MHz or 1.4 MHz, having a controlled frequency variation over the input voltage range. As the
load current decreases, the converter enters power save mode, reducing the switching frequency and minimizing
the IC quiescent current to achieve high efficiency over the entire load current range. DCS-Control supports both
operation modes (PWM and PFM) using a single building block with a seamless transition from PWM to power
save mode without effecting the output voltage. The TPS62090Q device offers excellent DC-voltage regulation
and load transient regulation, combined with low output voltage ripple, to minimize interference with RF circuits.
7.2 Functional Block Diagram
(2) The resistors are disconnected when the pins are high.
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7.3 Feature Description
7.3.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin
is pulled low with a shutdown current of typically 0.6 µA. In shutdown mode, the internal power switches as well
as the entire control circuitry are turned off. An internal resistor of 200 Ω discharges the output through the VOS
pin smoothly. An internal pulldown resistor of 400 is connected to the EN pin when the EN pin is low. The
pulldown resistor is disconnected when the EN pin is high.
7.3.2 Soft Start (SS) and Hiccup Current Limit During Start-Up
To minimize inrush current during start-up, the device has an adjustable soft start depending on the capacitor
value connected to the SS pin. The device charges the soft-start capacitor with a constant current of typically
7.5 µA. The feedback voltage follows this voltage with a fraction of 1.56 until the internal reference voltage of
0.8 V is reached. The soft-start operation is complete when the voltage at the soft-start capacitor has reached
typically 1.25 V. The soft-start time is calculated using Equation 1. The larger the soft-start capacitor, the longer
the soft-start time. The relation between soft-start voltage and feedback voltage is estimated using Equation 2.
SS SS
1.25V
t = C x 7.5μA
(1)
SS
FB
V
V =
1.56
(2)
During start-up, the switch current limit is reduced to 1/3 (approximately 1.5 A) of its typical current limit of 4.6
A. Once the output voltage exceeds typically 0.6 V, the current limit is released to its nominal value. The device
provides a reduced load current of approximately 1.5 A when the output voltage is below typically 0.6 V. Due
to this, a small or no soft-start time may trigger the short-circuit protection during start-up especially for larger
output capacitors. This is avoided by using a larger soft-start capacitance to extend the soft-start time. See
Section 7.3.4 for details of the reduced current limit during start-up. Leaving the soft-start pin floating sets the
minimum start-up time (around 50 µs).
7.3.3 Voltage Tracking (SS)
The SS pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 7-1. The internal reference voltage follows the voltage at the SS pin with a fraction
of 1.56 until the internal reference voltage of 0.8 V is reached. The device achieves ratiometric or coincidental
(simultaneous) output tracking, as shown in Figure 7-2.
SS FB
R1
R2
GND
VOUT1
R3
R4
GND
VOUT2
Copyright © 2017, Texas Instruments Incorporated
Figure 7-1. Output Voltage Tracking
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TEXAS INSTRUMENTS Vuuage Vonage a) Raucmelnc Trackmg m Cmnmdema‘ Trackmg
Voltage
t
VOUT1
VOUT2
Voltage
t
VOUT1
VOUT2
a) Ratiometric Tracking b) Coincidental Tracking
56.1
1
2R
1R
1
4R
3R
1´
÷
ø
ö
ç
è
æ+<+
56.1
1
2R
1R
1
4R
3R
1´
÷
ø
ö
ç
è
æ+=+
Figure 7-2. Voltage Tracking Options
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5-µA soft start-up current
into account. 1 kΩ or smaller is a sufficient value for R2.
For decreasing the SS pin voltage, the device does not sink current from the output when the device is in power
save mode. So the resulting decreases of the output voltage may be slower than the SS pin voltage if the load is
light. When driving the SS pin with an external voltage, do not exceed the voltage rating of the SS pin which is
7 V.
7.3.4 Short-Circuit Protection (Hiccup Mode)
The device is protected against hard short circuits to GND and overcurrent events. This protection is
implemented by a two-level short-circuit protection. During start-up and when the output is shorted to GND,
the switch current limit is reduced to 1/3 of the typical current limit of 4.6 A. When the output voltage exceeds
typically 0.6 V, the current limit is released to the nominal value. The full current limit is implemented as a hiccup
current limit. Once the internal current limits are triggered 32 times, the device stops switching and starts a new
start-up sequence after a typical delay time of 66 µS passed by. The device continues in this cycle until the high
current condition is released.
7.3.5 Output Discharge Function
To ensure the device starts up under the defined conditions, the output discharges through the VOS pin with a
typical discharge resistor of 200 Ω whenever the device shuts down. This discharge happens when the device is
disabled or if thermal shutdown, undervoltage lockout or short-circuit hiccup mode is triggered.
7.3.6 Power Good Output (PG)
The power good output is low when the output voltage is below the nominal value. The power good becomes
high impedance once the output is within 5% of regulation. The PG pin is an open-drain output and is specified
to typically sink up to 1 mA. This output requires a pullup resistor to be monitored properly. The pullup resistor
cannot be connected to any voltage higher than the input voltage of the device. The PG output is low when the
device is disabled, in thermal shutdown, or in UVLO. The PG output can be left floating if unused.
7.3.7 Frequency Set Pin (FREQ)
The FREQ pin is a digital logic input which sets the nominal switching frequency. Pulling this pin to GND sets the
nominal switching frequency to 2.8 MHz and pulling this pin high sets the nominal switching frequency to
1.4 MHz. Because this pin changes the switching frequency, it also changes the on-time during PFM mode. At
1.4 MHz the on-time is twice the on-time as operating at 2.8 MHz. This pin has an active pulldown resistor of
typically 400 kΩ. For applications where efficiency is of highest importance, a lower switching frequency should
be selected. A higher switching frequency allows the use of smaller external components, faster load transient
response, and lower output voltage ripple when using same L-C values.
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7.3.8 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 2.2 V with a 200-mV hysteresis.
7.3.9 Thermal Shutdown
The device enters thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C
hysteresis.
7.3.10 Charge Pump (CP, CN)
The CP and CN pins must attach to an external 10-nF capacitor to complete a charge pump for the gate driver.
This capacitor must be rated for the input voltage. TI does not recommend connecting any other circuits to the
CP or CN pins.
7.4 Device Functional Modes
7.4.1 Pulse Width Modulation Operation
At medium to heavy load currents, the device operates with PWM at a nominal switching frequency of 2.8 MHz
or 1.4 MHz depending on the setting of the FREQ pin. As the load current decreases, the converter enters
the power save mode operation reducing the switching frequency. The device enters power save mode at the
boundary to discontinuous conduction mode (DCM).
7.4.2 Power Save Mode Operation
As the load current decreases, the converter enters power save mode operation. During power save mode, the
converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current while
maintaining high efficiency. The power save mode is based on a fixed on-time architecture following Equation 3.
When operating at 1.4 MHz, the on-time is twice as long as the on-time for 2.8-MHz operation, resulting in larger
output voltage ripple, as shown in Figure 8-11 and Figure 8-12, and slightly higher output voltage at no load, as
shown in Figure 8-8 and Figure 8-9. To have the same output voltage ripple at 1.4 MHz during PFM mode, either
the output capacitor or the inductor value must be increased. As an example, operating at 2.8 MHz using
0.47-µH inductor gives the same output voltage ripple as operating with 1.4 MHz using 1-µH inductor.
2.8MHz
1.4MHz
2
VOUT
ton = × 360ns
V
IN
VOUT
ton = × 360ns × 2
V
IN
2 × IOUT
=
V - V V - V
IN IN
OUT OUT
ton 1 + x
V L
OUT
fæ ö
ç ÷
ç ÷
è ø
(3)
In power save mode the output voltage rises slightly above the nominal output voltage in PWM mode, as shown
in Figure 8-8 and Figure 8-9. This effect is reduced by increasing the output capacitance or the inductor value.
This effect is also reduced by programming the output voltage of the TPS62090Q lower than the target value.
As an example, if the target output voltage is 3.3 V, then the TPS62090Q is programmed to 3.3 V 0.8%. As a
result the output voltage accuracy is now –2.2% to +2.2% instead of –1.4% to 3%. The output voltage accuracy
in PFM operation is reflected in the Section 6.5 table and given for a 22-µF output capacitance.
7.4.3 Low-Dropout Operation (100% Duty Cycle)
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the
high-side MOSFET switch is constantly turned on which is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage where the output voltage falls below the nominal regulation value is given by Equation 4.
VIN (min) = VOUT + IOUT × ( RDS(on) + RL ) (4)
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Where
• RDS(on) = High side FET on-resistance
• RL = DC resistance of the inductor
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS62090-Q1 device is a high-frequency, synchronous, step-down converter optimized for small solution
size, high efficiency, and is suitable for battery-powered applications.
8.2 Typical Application
R1
200 k
R2
160 k
C2
22 µF
R3
500 k
C1
10 µF
VIN
2.5 V to 6 V
VPG
VOUT
1.8 V / 3.0 A
L1
470 nH
TPS62090Q
C3
10 nF
C4
10 nF
VOUT
SS
PVIN
PVIN
AVIN
EN
CP
CN
AGND
SW
SW
VOS
FB
PG
FREQ
PGND PGND
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Test Circuit
8.2.1 Design Requirements
Table 8-1 is a recommended list of components for the test circuit in Figure 8-1.
Table 8-1. List of Components
REFERENCE DESCRIPTION MANUFACTURER
TPS62090Q High efficiency step-down converter Texas Instruments
L1 Inductor: 1 µH, 0.47 µH, 0.4 µH Coilcraft XFL4020-102, XAL4020-401, TOKO DEF252012-R47
C1 Ceramic capacitor: 10 µF, 22 µF (6.3-V, X5R, 0603), (6.3-V, X5R, 0805)
C2 Ceramic capacitor: 22 µF (6.3-V, X5R, 0805)
C3, C4 Ceramic capacitor Standard
R1, R2, R3 Resistor Standard
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8.2.2 Detailed Design Procedure
The first step in the design procedure is the selection of the output filter components. To simplify this process,
Table 8-2 and Table 8-3 list possible inductor and capacitor value combinations.
Table 8-2. Output Filter Selection (2.8-MHz Operation, FREQ = GND)
INDUCTOR VALUE (µH)(3) OUTPUT CAPACITOR VALUE (µF)(2)
10 22 47 100 150
0.47 — √(1) √√√
1 √√√√√
2.2 — — — — —
3.3 — — — — —
(1) Typical application configuration. Other check marks indicate alternative filter combinations.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance varies by
+20% and –50%.
(3) Inductor tolerance and current de-rating is anticipated. The effective inductance varies by +20%
and –30%.
Table 8-3. Output Filter Selection (1.4-MHz Operation, FREQ = VIN)
INDUCTOR VALUE (µH)(3) OUTPUT CAPACITOR VALUE (µF)(2)
10 22 47 100 150
0.47 √ √ √ √
1 √ √(1) √√√
2.2 √ √ √ √ √
3.3 — — — — —
(1) Typical application configuration. Other check marks indicate alternative filter combinations.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance varies by
+20% and –50%.
(3) Inductor tolerance and current de-rating is anticipated. The effective inductance varies by +20%
and –30%.
8.2.2.1 Inductor Selection
The inductor selection is affected by several parameters such as inductor-ripple current, output-voltage ripple,
transition point into power save mode, and efficiency. See Table 8-4 for typical inductors.
Table 8-4. Inductor Selection
INDUCTOR VALUE COMPONENT SUPPLIER SIZE (L × W × H mm) Isat / DCR
0.6 µH Coilcraft XAL4012-601 4 × 4 × 2.1 7.1 A / 9.5 mΩ
1 µH Coilcraft XAL4020-102 4 × 4 × 2.1 5.9 A / 13.2 mΩ
1 µH Coilcraft XFL4020-102 4 × 4 × 2.1 5.1 A / 10.8 mΩ
0.47 µH TOKO DFE252012 R47 2.5 × 2 × 1.2 3.7 A / 39 mΩ
1 µH TOKO DFE252012 1R0 2.5 × 2 × 1.2 3.0 A / 59 mΩ
0.68 µH TOKO DFE322512 R68 3.2 × 2.5 × 1.2 3.5 A / 37 mΩ
1 µH TOKO DFE322512 1R0 3.2 × 2.5 × 1.2 3.1 A / 45 mΩ
In addition, the inductor must be rated for the appropriate saturation current and DC resistance (DCR). The
inductor must be rated for a saturation current as high as the typical switch current limit, of 4.6 A or according
to Equation 5 and Equation 6. Equation 5 and Equation 6 calculate the maximum inductor current under static
load conditions. The formula takes the converter efficiency into account. The converter efficiency is taken from
the Section 6.6 graphs or 80% can be used as a conservative approach. The calculation must be done for the
maximum input voltage where the peak switch current is highest.
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ΔIL
I = I +
LOUT 2
(5)
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V V
OUT OUT
x 1 -
η V x η
IN
I = I +
LOUT 2 x x Lf
æ ö
ç ÷
ç ÷
è ø
(6)
where
ƒ = Converter switching frequency (typical 2.8 MHz or 1.4 MHz)
L = Selected inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as an conservative
assumption)
Note
The calculation must be done for the maximum input voltage of the application
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of 20% must be added to cover for load transients during operation.
8.2.2.2 Input and Output Capacitor Selection
For best output and input voltage filtering, low-ESR (X5R or X7R) ceramic capacitors are recommended. The
input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail
for the device. A 10-µF or larger input capacitor is recommended when FREQ = Low and a 22-µF or larger when
FREQ = High.
The output capacitor value can range from 10 µF up to 150 µF and beyond. Load transient testing and
measuring the bode plot are good ways to verify stability with larger capacitor values. The recommended
typical output capacitor value is 22 µF (nominal) and can vary over a wide range as outline in the output filter
selection table. For output voltages above 1.8 V, noise can cause duty cycle jitter. This does not degrade device
performance. Using an output capacitor of 2 × 22 µF (nominal) for output voltages >1.8 V avoids duty cycle jitter.
Ceramic capacitor have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating.
8.2.2.3 Setting the Output Voltage
The output voltage is set by an external resistor divider according to Equation 7, Equation 8, and Equation 9.
OUT FB
R1 R1
V = V 1 + = 0.8 V 1 +
R2 R2
æ ö æ ö
´ ´
ç ÷ ç ÷
è ø è ø
(7)
FB
FB
V0.8 V
R2 = = 160 kΩ
I 5 μA
»
(8)
OUT OUT
FB
V V
R1 = R2 1 = R2 1
V 0.8V
æ ö æ ö
´ - ´ -
ç ÷ ç ÷
è ø
è ø
(9)
When sizing R2, use a minimum of 5 µA for the feedback current (IFB) to achieve low quiescent current and
acceptable noise sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. A
feed-forward capacitor is not required for proper operation.
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8.2.3 Application Curves
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 3.3 V
L = 1 µH
f = 1.4 MHz
G002
Figure 8-2. Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 3.3 V
L = 1 µH
f = 2.8 MHz
G001
Figure 8-3. Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
G003
Figure 8-4. Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
G004
Figure 8-5. Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.05 V
L = 1.0 µH
f = 1.4 MHz
G005
Figure 8-6. Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
100
100m 1 10 100 1k 10k
I load (mA)
Efficiency (%)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.05 V
L = 0.4 µH
f = 2.8 MHz
G006
Figure 8-7. Efficiency vs Load Current
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I TEXAS INSTRUMENTS 400 ns/dlv 5m 1 us/dlv 1 waw ‘ zoo us/dlv 5 200 us/dw a
1.79
1.795
1.8
1.805
1.81
1.815
1.82
1.825
1.83
100m 1 10 100 1k 10k
I load (mA)
Output Voltage (V)
VIN = 5.0 V
VIN = 4.2 V
VIN = 3.7 V
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
G007
Figure 8-8. Output Voltage vs Load Current
1.79
1.795
1.8
1.805
1.81
1.815
1.82
1.825
1.83
100m 1 10 100 1k 10k
I load (mA)
Output Voltage (V)
VIN = 5.0 V
VIN = 4.2 V
VIN = 3.7 V
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
G008
Figure 8-9. Output Voltage vs Load Current
V
2 V/div
sw
V
20 mV/div
o
I
1 A/div
inductor
V
V =1.8 V/3 A
f = 1.4 MHz, L = 1 µH
in
o
= 3.7 V
400 ns/div G012
Figure 8-10. PWM Operation
V
2 V/div
sw
V
20 mV/div
o
I
500 mA/div
inductor
V
V = 1.8 V/100 mA
f = 1.4 MHz, L = 1 µH
in
o
= 3.7 V
1 µs/div G013
Figure 8-11. PFM Operation
V
2 V/div
sw
V
20 mV/div
o
I
500 mA/div
inductor
V
V = 1.8 V/100 mA
f = 2.8 MHz, L = 0.47 µH
in
o
= 3.7 V
1 µs/div G014
Figure 8-12. PFM Operation
I
1 A/div
o
V
20 mV/div
o
I
500 mA/div
inductor
V
V = 1.8 V
f = 1.4 MHz, L = 1 µH
in
o
= 3.7 V
200 µs/div G015
Figure 8-13. Load Sweep
I
2 A/div
o
V
20 mV/div
o
I
500 mA/div
inductor
V
V = 1.8 V
f = 2.8 MHz, L = 1 µH
in
o
= 3.7 V
200 µs/div G016
Figure 8-14. Load Sweep
V
1 V/div
o
V
2 V/div
EN
I
500 mA/div
inductor
400 µs/div G017
VO = 1.8 V / 600 mA f = 2.8 MHz / L = 1 µH CSS = 10 nF
Figure 8-15. Start-Up
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V
1 V/div
o
V
2 V/div
EN
I
500 mA/div
inductor
2 ms/div G018
VO = 1.8 V / No Load f = 1.4 MHz / L = 1 µH
Figure 8-16. Shutdown
V
1 V/div
o
I
2 A/div
o
I
1 A/div
inductor
V
V = 1.8 V
f = 1.4 MHz, L = 1 µH
in
o
= 3.7 V
40 µs/div G019
Figure 8-17. Hiccup Short-Circuit Protection
V
1 V/div
o
I
2 A/div
o
I
1 A/div
inductor
V
V = 1.8 V
f = 1.4 MHz, L = 1 µH
in
o
= 3.7 V
400 µs/div G020
Figure 8-18. Hiccup Short-Circuit Protection
V
50 mV/div
o
I
1 A/div
o
I
1 A/div
inductor
4 µs/div G021
V
V = 1.8 V,0.3 A to 2.5 A
f = 1.4 MHz, L = 1 µH
C = 22 µF
in
o
o
= 3.7 V
Figure 8-19. Load Transient Response
V
50 mV/div
o
I
1 A/div
inductor
40 µs/div G022
V
V = 1.8 V, 0.3 A to 2.5 A
f = 1.4 MHz, L = 1 µH
C = 22 µF
in
o
o
= 3.7 V
Figure 8-20. Load Transient Response
V
50 mV/div
o
I
1 V/div
o
I
500 A/div
inductor
100 µs/div G023
V
V = 1.8 V, 20 mA to 1 A
f = 1.4 MHz, L = 1 µH
C = 22 µF
in
o
o
= 3.7 V
Figure 8-21. Load Transient Response
8.3 System Examples
Figure 8-22, Figure 8-23, and Figure 8-24 show additional circuits for varying voltage options.
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Vout
1.5 V / 3 A
Vin
2.5 to 6 V PVIN
PVIN
EN FB
C1
10 Fm
L1
470 nH
C2
22 Fm
R1
140 k
SW
TPS6209x-Q1
SW
Power Good
AVIN
R2
160 k
SS
R3
500 k
AGND
PG
C4
10 nF
VOS
FREQ
CP
CN
C3
10 nF
1
2
3
4
5
6
PGND PGND
7
8
9
10
11
12
13
14 15
16
Copyright © 2016, Texas Instruments Incorporated
Figure 8-22. 1.5-V Adjustable Version Operating at 2.8 MHz
Vout
1.8 V / 3 A
Vin
2.5 to 6 V PVIN
PVIN
EN FB
C1
22 mF
L1
1mH
C2
22 mF
R1
200 kSW
TPS6209x-Q1
SW
Power Good
AVIN
R2
160 k
SS
R3
500 k
AGND
PG
C4
10 nF
VOS
FREQ
CP
CN
C3
10 nF
1
2
3
4
5
6
PGND PGND
7
8
9
10
11
12
13
14 15
16
Vin
Copyright © 2016, Texas Instruments Incorporated
Figure 8-23. 1.8-V Adjustable Version Operating at 1.4 MHz
Vout
1.05 V / 3 A
Vin
2.5 to 6 V PVIN
PVIN
EN FB
C1
22 mF
L1
1mH
C2
22 mF
R1
68 kSW
TPS6209x-Q1
SW
Power Good
AVIN
R2
220 k
SS
R3
500 k
AGND
PG
C4
10 nF
VOS
FREQ
CP
CN
C3
10 nF
1
2
3
4
5
6
PGND PGND
7
8
9
10
11
12
13
14 15
16
Vin
Copyright © 2016, Texas Instruments Incorporated
Figure 8-24. 1.05-V Adjustable Version Operating at 1.4 MHz
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9 Power Supply Recommendations
The power supply to the TPS62090-Q1 device must have a current rating according to the supply voltage, output
voltage, and output current of the TPS62090-Q1 device.
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10 Layout
10.1 Layout Guidelines
TI recommends placing the input capacitor as close as possible to the IC pins PVIN and PGND.
The VOS connection is noise sensitive and needs to be routed as short and directly to the output pin of the
inductor.
The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a
single joint connection at the exposed thermal pad of the package. This minimizes switch node jitter.
The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling
of switching waveforms into other traces and circuits.
Refer to the TPS62090EVM-063 Evaluation Module (SLVU670) for an example of component placement,
routing, and thermal design.
10.2 Layout Example
R2x1
L1x1
GND
VIN
VOUT
PGND
PGND
VOS
EN
AGND
CP
FB
CN
AVIN
PVIN
SS
PVIN
FREQ
SW
PG
SW
L1
C1
C2
C4
C5
R2
R1
AGND
Figure 10-1. TPS62090Q Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Basic Calculation of a Buck Converter's Power Stage (SLVA477)
Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs (SLVA485)
How to Measure the Control Loop of DCS-Control™ Devices (SLVA465)
Optimizing the TPS62090 Output Filter (SLVA519)
Performing Accurate PFM Mode Efficiency Measurements (SLVA236)
QFN/SON PCB Attachment (SLUA271)
TPS62090EVM-063 Evaluation Module (SLVU670)
Understanding the Absolute Maximum Ratings of the SW Node (SLVA494)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E support forums are an engineer's go-to source for fast, verified answers and design help straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
DCS-Control and TI E2E are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS62090QRGTRQ1 ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SJG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
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of the previous line and the two combined represent the entire Device Marking for that device.
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lines if the finish value exceeds the maximum column width.
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OTHER QUALIFIED VERSIONS OF TPS62090-Q1 :
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2021
Addendum-Page 2
Catalog : TPS62090
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62090QRGTRQ1 VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Nov-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62090QRGTRQ1 VQFN RGT 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Nov-2021
Pack Materials-Page 2
GENERIC PACKAGE VIEW RGT 16 VQFN - 1 mm max heigm PLASTIC QUAD FLATPACKV N0 LEAD Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4203495” I TEXAS INSTRI IMFNTS
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