October 2017
DocID15676 Rev 7
1/29
This is information on a product in full production.
www.st.com
LD39100
1 A, low quiescent current, low-noise voltage regulator
Datasheet - production data
Features
AEC-Q100 qualified
Input voltage from 1.5 to 5.5 V
Ultra-low dropout voltage (200 mV typ. at
1 A load)
Very low quiescent current (20 µA typ. at no
load, 200 µA typ. at 1 A load, 1 µA max. in
off mode)
Very low-noise with no bypass capacitor
(30 µ VRMS at VOUT = 0.8 V)
Output voltage tolerance: ±2.0% at 25 °C
1 A guaranteed output current
Wide range of output voltages available on
request: 0.8 V to 4.5 V with 100 mV step and
adjustable from 0.8 V
Logic-controlled electronic shutdown
Stable with ceramic capacitors COUT = 1 µF
Internal current and thermal limit
DFN6 (3x3 mm) package
Temperature range: -40 °C to 125 °C
Applications
Printers
Game consoles
Computer
Consumer applications
Automotive post regulation
Description
The LD39100 provides 1 A maximum current with
an input voltage range from 1.5 V to 5.5 V and a
typical dropout voltage of 200 mV. The device is
stable with ceramic capacitors on the input and
output. The ultra-low dropout voltage, low
quiescent current and low-noise features make it
suitable for low power battery-powered
applications. Power supply rejection is 70 dB at
low frequency and starts to roll off at 10 kHz.
Enable logic control function puts the LD39100 in
shutdown mode, allowing a total current
consumption lower than 1 µA. The device also
includes short-circuit constant current limiting and
thermal protection. LD39100 is available also in
AEC-Q100 qualified version, in the DFN6
(3x3 mm) with wettable flank package.
DFN6 (3x3 mm)
Contents
LD39100
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DocID15676 Rev 7
Contents
1 Circuit schematics........................................................................... 5
2 Pin configuration ............................................................................. 6
3 Maximum ratings ............................................................................. 7
4 Electrical characteristics ................................................................ 8
5 Typical performance characteristics ........................................... 12
6 Application information ................................................................ 16
6.1 External capacitors .......................................................................... 17
6.1.1 Input capacitor .................................................................................. 17
6.1.2 Output capacitor ............................................................................... 17
6.2 Power dissipation ............................................................................ 17
6.3 Enable function ............................................................................... 18
6.4 Power Good function ....................................................................... 18
7 Package information ..................................................................... 20
7.1 DFN6 (3x3 mm) package information ............................................. 21
7.2 DFN6 (3x3 mm) automotive-grade package information ................. 23
7.3 DFN6 (3x3 mm) packing information ............................................... 25
8 Ordering information ..................................................................... 27
9 Revision history ............................................................................ 28
LD39100
List of tables
DocID15676 Rev 7
3/29
List of tables
Table 1: Pin description .............................................................................................................................. 6
Table 2: Absolute maximum ratings ........................................................................................................... 7
Table 3: Thermal data ................................................................................................................................. 7
Table 4: ESD performance ......................................................................................................................... 7
Table 5: LD39100 electrical characteristics (adjustable version) ............................................................... 8
Table 6: LD39100 electrical characteristics (fixed version) ...................................................................... 10
Table 7: DFN6 (3x3 mm) mechanical data ............................................................................................... 22
Table 8: DFN6 (3x3 mm) automotive-grade mechanical data .................................................................. 24
Table 9: DFN6 (3x3) tape and reel mechanical data ................................................................................ 26
Table 10: Order code ................................................................................................................................ 27
Table 11: Document revision history ........................................................................................................ 28
List of figures
LD39100
4/29
DocID15676 Rev 7
List of figures
Figure 1: LD39100 schematic diagram (adjustable version) ...................................................................... 5
Figure 2: LD39100 schematic diagram (fixed version) ............................................................................... 5
Figure 3: Pin connection (top view) ............................................................................................................ 6
Figure 4: VADJ accuracy ............................................................................................................................ 12
Figure 5: VOUT accuracy ............................................................................................................................ 12
Figure 6: Dropout voltage vs. temperature (VOUT = 2.5 V) ........................................................................ 12
Figure 7: Dropout voltage vs. temperature (VOUT = 1.5 V) ........................................................................ 12
Figure 8: Dropout voltage vs. output current ............................................................................................ 12
Figure 9: Short-circuit current vs. drop voltage ......................................................................................... 12
Figure 10: Output voltage vs. input voltage (VOUT = 0.8 V) ....................................................................... 13
Figure 11: Output voltage vs. input voltage (VOUT = 2.5 V) ....................................................................... 13
Figure 12: Quiescent current vs. temperature .......................................................................................... 13
Figure 13: VIN input current in off mode vs. temperature .......................................................................... 13
Figure 14: Load regulation ........................................................................................................................ 13
Figure 15: Line regulation VOUT = 0.8 V .................................................................................................... 13
Figure 16: Line regulation VOUT = 2.5 V .................................................................................................... 13
Figure 17: Supply voltage rejection vs. temperature (VOUT = 0.8 V) ......................................................... 13
Figure 18: Supply voltage rejection vs. temperature (VOUT = 2.5 V) ......................................................... 14
Figure 19: Supply voltage rejection vs. frequency (VOUT = 0.8 V) ............................................................ 14
Figure 20: Supply voltage rejection vs. frequency (VOUT = 2.5 V) ............................................................ 14
Figure 21: Output noise voltage vs. frequency ......................................................................................... 14
Figure 22: Enable voltage vs. temperature ............................................................................................... 14
Figure 23: Load Transient (VOUT = 0.8 V, IOUT = from 10 mA to 1 A) ........................................................ 14
Figure 24: Load Transient (VOUT = 0.8 V, IOUT = from 100 mA to 1 A) ...................................................... 15
Figure 25: Load Transient (VOUT = 2.5 V, IOUT = from 10 mA to 1 A) ........................................................ 15
Figure 26: Load Transient (VOUT = 2.5 V, IOUT = from 100 mA to 1 A) ...................................................... 15
Figure 27: Line transient ........................................................................................................................... 15
Figure 28: Start-up transient ..................................................................................................................... 15
Figure 29: Enable transient ....................................................................................................................... 15
Figure 30: Typical application circuit for fixed output version ................................................................... 16
Figure 31: Typical application circuit for adjustable version ..................................................................... 16
Figure 32: Power dissipation vs. ambient temperature ............................................................................ 18
Figure 33: DFN6 (3x3 mm) package outline ............................................................................................. 21
Figure 34: DFN6 (3x3 mm) recommended footprint ................................................................................. 22
Figure 35: DFN6 (3x3 mm) automotive-grade package outline ............................................................... 23
Figure 36: DFN6 (3x3 mm) automotive-grade recommended footprint .................................................... 24
Figure 37: DFN6 (3x3) tape outline .......................................................................................................... 25
Figure 38: DFN6 (3x3 mm) reel outline .................................................................................................... 26
PG:
Power-good
slg nal
IN
IN
{131
our
D
GND
EN
PG‘
Power-good
signal
GND
LD39100
Circuit schematics
DocID15676 Rev 7
5/29
1 Circuit schematics
Figure 1: LD39100 schematic diagram (adjustable version)
Figure 2: LD39100 schematic diagram (fixed version)
Current
limit
Thermal
protection
OUT
GND
OpAmp
IN Power-good
signal
PG
Internal
enable
IN
ADJ
EN
BandGap
reference Current
limit
Thermal
protection
OUT
GND
OpAmp
IN Power-good
signal
PG
Internal
enable
ININ
ADJ
EN
BandGap
reference
GIPD010920151332MT
Current
limit
Thermal
protection
OUT
GND
OpAmp
IN Power-good
signal
PG
Internal
enable
IN
NC
EN
BandGap
reference
R1
R2
Current
limit
Thermal
protection
OUT
GND
OpAmp
IN Power-good
signal
PG
Internal
enable
ININ
NC
EN
BandGap
reference
R1
R2
GIPD010920151333MT
flflfl
Pin configuration
LD39100
6/29
DocID15676 Rev 7
2 Pin configuration
Figure 3: Pin connection (top view)
Table 1: Pin description
Symbol
Pin
Function
LD39100 (adjustable
version)
LD39100 (fixed
version)
EN
1
1
Enable pin logic input: low = shutdown,
high = active
GND
2
2
Common ground
PG
3
3
Power Good
VOUT
4
4
Output voltage
ADJ
5
-
Adjust pin
VIN
6
6
LDO input voltage
NC
-
5
Not connected
GND
Exposed pad
Exposed pad has to be connected to
GND
LD39100 (fixedversion)
EN
GND
PG
VIN
NC
VOUT
EN
GND
PG
VIN
ADJ
VOUT
LD39100 (adjustable version)
1
2
34
5
6 1
2
34
5
6
GIPD010920151334MT
LD39100
Maximum ratings
DocID15676 Rev 7
7/29
3 Maximum ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VIN
DC input voltage
-0.3 to 7
V
VOUT
DC output voltage
-0.3 to VIN + 0.3
(7 V max.)
V
EN
Enable pin
-0.3 to VIN + 0.3
(7 V max.)
V
PG
Power Good pin
-0.3 to 7
V
ADJ
Adjust pin
4
V
IOUT
Output current
Internally limited
PD
Power dissipation
Internally limited
TSTG
Storage temperature range
- 65 to 150
°C
TOP
Operating junction temperature range
- 40 to 125
°C
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. All values
are referred to GND.
Table 3: Thermal data
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction-ambient
55
°C/W
RthJC
Thermal resistance junction-case
10
°C/W
Table 4: ESD performance
Symbol
Parameter
Test conditions
Value
Unit
ESD
ESD protection voltage
HBM
4
kV
MM
0.4
kV
Electrical characteristics
LD39100
8/29
DocID15676 Rev 7
4 Electrical characteristics
TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise
specified.
Table 5: LD39100 electrical characteristics (adjustable version)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIN
Operating input
voltage
1.5
5.5
V
VADJ
VADJ accuracy
IOUT = 10 mA
TJ = 25 °C
784
800
816
mV
IOUT = 10 mA
-40 °C < TJ < 125 °C
776
800
824
IADJ
Adjust pin current
1
µA
∆VOUT
Static line
regulation
VOUT + 1 V ≤ VIN ≤ 5.5 V
IOUT = 100 mA
0.01
%/V
∆VOUT
Transient line
regulation (1)
∆VIN = 500 mV
IOUT = 100 mA
tR = 5 µs
10
mVpp
∆VIN = 500 mV
IOUT = 100 mA
tF = 5 µs
10
∆VOUT
Static load
regulation
IOUT = 10 mA to 1 A
0.002
%/mA
∆VOUT
Transient load
regulation (1)
IOUT = 10 mA to 1 A
tR = 5 µs
40
mVpp
IOUT = 1 A to 10 mA
tF = 5 µs
40
VDROP
Dropout voltage (2)
IOUT = 1 A VO fixed to 1.5 V
-40 °C < TJ < 125 °C
200
400
mV
eN
Output noise
voltage
10 Hz to 100 kHz
IOUT = 100 mA
VOUT = 0.8 V
30
µVRMS
SVR
Supply voltage
rejection VO = 0.8 V
VIN = 1.8 V+/-VRIPPLE
VRIPPLE = 0.25 V
frequency = 1 kHz
IOUT = 10 mA
70
dB
VIN = 1.8 V+/-VRIPPLE VRIPPLE = 0.25 V
frequency = 10 kHz
IOUT = 100 mA
65
IQ
Quiescent current
IOUT = 0 mA
20
µA
IOUT = 0 mA -40 °C < TJ < 125 °C
50
IOUT = 0 to 1 A
200
LD39100
Electrical characteristics
DocID15676 Rev 7
9/29
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IQ
Quiescent current
IOUT = 0 to 1 A
-40 °C < TJ < 125 °C
300
µA
VIN input current in off mode:
VEN = GND (3)
0.001
1
PG
Power good output
threshold
Rising edge
0.92*
VOUT
V
Falling edge
0.8*
VOUT
Power good output
voltage low
Isink = 6 mA open drain output
0.4
V
ISC
Short-circuit current
RL= 0
2.5
A
VEN
Enable input logic
low
VIN = 1.5 V to 5.5 V
-40 °C < TJ< 125 °C
0.4
V
Enable input logic
high
0.9
V
IEN
Enable pin input
current
VEN = VIN
0.1
100
nA
tON
Turn-on time (4)
30
µs
TSHDN
Thermal shutdown
160
°C
Hysteresis
20
COUT
Output capacitor
Capacitance (seeSection 5: "Typical
performance characteristics")
1
µF
Notes:
(1)All transient values are guaranteed by design, not tested in production.
(2)Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal
value. This specification does not apply to output voltages below 1.5 V.
(3)PG pin floating.
(4)Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage
just reaching 95% of its nominal value.
Electrical characteristics
LD39100
10/29
DocID15676 Rev 7
TJ = 25 °C, VIN = VOUT(NOM) + 1 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless
otherwise specified.
Table 6: LD39100 electrical characteristics (fixed version)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VI
Operating input
voltage
1.5
5.5
V
VOUT
VOUT accuracy
VOUT >1.5 V
IOUT = 10 mA
TJ = 25 °C
-2.0
2.0
%
VOUT > 1.5 V
IOUT = 10 mA
-40 °C < TJ < 125 °C
-3.0
3.0
VOUT ≤ 1.5 V
IOUT = 10 mA
±20
mV
VOUT ≤ 1.5 V
IOUT = 10 mA
-40 °C < TJ < 125 °C
±30
∆VOUT
Static line
regulation
VOUT + 1 V ≤ VIN ≤ 5.5 V
IOUT = 100 mA
0.01
%/V
∆VOUT
Transient line
regulation (1)
∆VIN = 500 mV
IOUT = 100 mA tR = 5 µs
10
mVpp
∆VIN = 500 mV
IOUT = 100 mA
tF = 5 µs
10
∆VOUT
Static load
regulation
IOUT = 10 mA to 1 A
0.002
%/mA
∆VOUT
Transient load
regulation (1)
IOUT = 10 mA to 1 A
tR = 5 µs
40
mVpp
IOUT = 1 A to 10 mA
tF = 5 µs
40
VDROP
Dropout voltage (2)
IOUT = 1 A VOUT > 1.5 V
-40 °C < TJ < 125 °C
200
400
mV
eN
Output noise
voltage
10 Hz to 100 kHz
IOUT = 100 mA VOUT = 2.5 V
85
µVRMS
SVR
Supply voltage
rejection
VOUT = 1.5 V
VIN = VOUT(NOM)+0.5 V+/-VRIPPLE
VRIPPLE = 0.1 V
frequency = 1 kHz
IOUT = 10 mA
65
dB
VIN = VOUT(NOM)+0.5 V+/-VRIPPLE
VRIPPLE = 0.1 V
frequency = 10 kHz
IOUT = 100 mA
62
LD39100
Electrical characteristics
DocID15676 Rev 7
11/29
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IQ
Quiescent current
IOUT = 0 mA
20
µA
IOUT = 0 mA
-40 °C < TJ < 125 °C
50
IOUT = 0 to 1 A
200
IOUT = 0 to 1 A
-40 °C < TJ < 125 °C
300
VIN input current in OFF mode: (3)
VEN = GND
0.001
1
PG
Power good output
threshold
Rising edge
0.92*
VOUT
V
Falling edge
0.8*
VOUT
Power good output
voltage low
Isink = 6 mA open drain output
0.4
V
ISC
Short-circuit current
RL = 0
2.5
A
VEN
Enable input logic
low
VIN = 1.5 V to 5.5 V
-40 °C < TJ < 125 °C
0.4
V
Enable input logic
high
0.9
V
IEN
Enable pin input
current
VEN = VIN
0.1
100
nA
TON
Turn-on time (4)
30
µs
TSHDN
Thermal shutdown
160
°C
Hysteresis
20
COUT
Output capacitor
Capacitance (see Section 5:
"Typical performance
characteristics")
1
µF
Notes:
(1)All transient values are guaranteed by design, not tested in production.
(2)Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal
value. This specification does not apply to output voltages below 1.5 V.
(3)PG pin floating.
(4)Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage
just reaching 95% of its nominal value.
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Typical performance characteristics
LD39100
12/29
DocID15676 Rev 7
5 Typical performance characteristics
CIN = COUT = 1 µF
Figure 4: VADJ accuracy
Figure 5: VOUT accuracy
Figure 6: Dropout voltage vs. temperature
(VOUT = 2.5 V)
Figure 7: Dropout voltage vs. temperature
(VOUT = 1.5 V)
Figure 8: Dropout voltage vs. output current
Figure 9: Short-circuit current vs. drop
voltage
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LD39100
Typical performance characteristics
DocID15676 Rev 7
13/29
Figure 10: Output voltage vs. input voltage
(VOUT = 0.8 V)
Figure 11: Output voltage vs. input voltage
(VOUT = 2.5 V)
Figure 12: Quiescent current vs. temperature
Figure 13: VIN input current in off mode vs.
temperature
Figure 14: Load regulation
Figure 15: Line regulation VOUT = 0.8 V
Figure 16: Line regulation VOUT = 2.5 V
Figure 17: Supply voltage rejection vs.
temperature (VOUT = 0.8 V)
GIPD020920151106MT
0
0.2
0.4
0.6
0.8
1
1.2
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VIN [V]
VOUT[V]
125°C
85°C
55°C
25°C
0°C
-25°C
-40°C
VIN from 0 to 5.5 V, VEN to VIN, VOUT = 0.8 V, IOUT = 1 A
125°C
85°C
55°C
25°C
0°C
-25°C
-40°C
VIN from 0 to 5.5 V, VEN to VIN, VOUT = 0.8 V, IOUT = 1 A
GIPD020920151107MT
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VIN [V]
VOUT[V]
125°C
85°C
55°C
25°C
0°C
-25°C
-40°C
VIN from 0 to 5V, VEN to VIN, VOUT = 2.5 V, IOUT =1A
VIN [V]
125°C
85°C
55°C
25°C
0°C
-25°C
-40°C
VIN from 0 to 5V, VEN to VIN, VOUT = 2.5 V, IOUT =1A
GIPD020920151108MT
0
20
40
60
80
100
120
140
-50 -25 0 25 50 75 100 125 150
T [°C]
Iq [µA]
No Load
IOUT = 1 A
VIN = 1.8 V, VEN to VIN, VOUT = 2.5 V
No Load
IOUT = 1 A
VIN = 1.8 V, VEN to VIN, VOUT = 2.5 V
GIPD020920151109MT
0
0.1
0.2
0.3
0.4
0.5
0.6
-50-25 0 25 5 0 75 100 125 150
T [°C ]
Iq[µA]
VIN = 3.5 V, VE N to GND, VO U T = 2.5 VVIN = 3.5 V, V E N to GND, VO U T = 2.5 V
GIPD020920151110MT
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
-50 -25 0 25 50 75 100 125 150
T [°C]
Load [%/mA]
VIN = 3.5 V, IOUT = from 10 mA to 1 A, VEN=VIN, VOUT = 2.5 VVIN = 3.5 V, IOUT = from 10 mA to 1 A, VEN=VIN, VOUT = 2.5 V
GIPD020920151111MT
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-50 -25 0 25 50 75 100 125150
T [°C]
VIN = from 1.8 V to 5.5 V , IOUT = 1 00 m A, VEN = V IN, VOUT = 0.8 V
Line [%/V]
VIN = from 1.8 V to 5.5 V , IOUT = 1 00 m A, VEN = V IN, VOUT = 0.8 V
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Typical performance characteristics
LD39100
14/29
DocID15676 Rev 7
Figure 18: Supply voltage rejection vs.
temperature (VOUT = 2.5 V)
Figure 19: Supply voltage rejection vs.
frequency (VOUT = 0.8 V)
Figure 20: Supply voltage rejection vs.
frequency (VOUT = 2.5 V)
Figure 21: Output noise voltage vs. frequency
Figure 22: Enable voltage vs. temperature
Figure 23: Load Transient (VOUT = 0.8 V,
IOUT = from 10 mA to 1 A)
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LD39100
Typical performance characteristics
DocID15676 Rev 7
15/29
Figure 24: Load Transient (VOUT = 0.8 V,
IOUT = from 100 mA to 1 A)
Figure 25: Load Transient (VOUT = 2.5 V,
IOUT = from 10 mA to 1 A)
Figure 26: Load Transient (VOUT = 2.5 V,
IOUT = from 100 mA to 1 A)
Figure 27: Line transient
Figure 28: Start-up transient
Figure 29: Enable transient
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Application information
LD39100
16/29
DocID15676 Rev 7
6 Application information
The LD39100 is an ultra low-dropout linear regulator. It provides up to 1 A with a low 200
mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available in fixed
and adjustable output versions.
The regulator is equipped with internal protection circuitry, such as short-circuit current
limiting and thermal protection.
Figure 30: "Typical application circuit for fixed output version" and Figure 31: "Typical
application circuit for adjustable version" illustrate the typical application schematics:
Figure 30: Typical application circuit for fixed output version
Figure 31: Typical application circuit for adjustable version
Regarding the adjustable version, the output voltage can be adjusted from 0.8 V up to the
input voltage, minus the voltage drop across the pass element (dropout voltage), by
connecting a resistor divider between ADJ pin and the output, thus allowing remote voltage
sensing.
LD39100
Application information
DocID15676 Rev 7
17/29
The resistor divider should be selected as follows:
Equation 1
Resistors should be used with values in the range from 10 kΩ to 50 kΩ. Lower values can
also be suitable, but they increase current consumption.
6.1 External capacitors
The LD39100 voltage regulator requires external low ESR capacitors to assure control loop
stability. These capacitors must be selected to meet the requirements of minimum
capacitance and equivalent series resistance defined in the following sections.
Input and output capacitors should be located as close as possible to the relevant pins.
6.1.1 Input capacitor
An input capacitor with a minimum value of 1 μF must be located as close as possible to
the input pin of the device and returned to a clean analog ground. A good quality, low-ESR
ceramic capacitor is suggested. It helps to ensure stability of the control loop, reduces the
effects of inductive sources and improves ripple rejection.
A value above 1 µF may be chosen when the application involves fast load transients.
6.1.2 Output capacitor
The LD39100 requires a low-ESR capacitor connected on its output to keep the control
loop stable and reduce the risk of ringing and oscillations. The control loop is designed to
be stable with any good quality ceramic capacitor (such as X5R/X7R types) with a
minimum value of 1 µF and equivalent series resistance in the 0 to 150 mΩ range.
It is important to highlight that the output capacitor must maintain its capacitance and ESR
in the stable region over the full operating temperature, load and input voltage ranges to
assure stability. Therefore, capacitance and ESR variations must be taken into account in
the design phase to ensure the device works in the expected stability region.
If the above conditions are respected, there is no maximum limit to the output capacitance.
6.2 Power dissipation
An internal thermal feedback loop disables the output voltage if the die temperature rises to
approximately 160 °C. This feature protects the device from excessive temperature and
allows the user to push the limits of the power handling capability of a given circuit board
without the risk of damaging the device.
A good PC board layout should be used to maximize power dissipation. The thermal path
for the heat generated by the device is from the die to the copper lead frame, through the
package leads and exposed pad, to the PC board copper. The PC board copper acts as a
heatsink. The footprint copper pads should be as wide as possible to spread and dissipate
the heat to the surrounding ambient. Feed-through vias to the inner or backside copper
layers are also useful to improve the overall thermal performance of the device.
VOUT = VADJ (1 + R1/ R2) with VADJ = 0.8 V (typ.)
Application information
LD39100
18/29
DocID15676 Rev 7
The device power dissipation depends on the input voltage, output voltage and output
current, and is given by:
Equation 2
Junction temperature of the device is:
Equation 3
where:
TJ_MAX is the maximum junction of the die,125 °C
TA is the ambient temperature
RthJA is the thermal resistance junction-to-ambient
Figure 32: Power dissipation vs. ambient temperature
6.3 Enable function
The LD39100 features the enable function. When EN voltage is higher than 0.9 V, the
device is ON, and if it is lower than 0.4 V, the device is OFF. In shutdown mode,
consumption is lower than 1 µA.
EN pin has not an internal pull-up, so it cannot be left floating if it is not used.
6.4 Power Good function
Some applications require a flag showing that the output voltage is in the correct range.
Power Good threshold depends on the adjust voltage. When it is higher than 0.92*VADJ,
Power Good (PG) pin goes to high impedance. If it is below 0.80*VADJ PG pin goes to low
PD= (VIN -VOUT) IOUT
TJ_MAX = TA+ RthJA x PD
0
0.5
1
1.5
2
2.5
3
3.5
-50 -30 -10 10 30 50 70 90 110130
TA[°C]
PD[W]
0
0.5
1
1.5
2
2.5
3
3.5
-50 -30 -10 10 30 50 70 90 110130
TA[°C]
PD[W]
GIPD040920151415MT
LD39100
Application information
DocID15676 Rev 7
19/29
impedance. If the device works well, Power Good pin is at high impedance. If the output
voltage is fixed using an external or internal resistor divider, Power Good threshold is
0.92*VOUT.
If the device is disabled (EN pin low) the PG signal is set to high impedance.This is done
intentionally to avoid pull down current by the PG pin in disabled mode.
Power Good function requires an external pull-up resistor, which has to be connected
between PG pin and VIN or VOUT. PG pin typical current capability is up to 6 mA. A pull-up
resistor for PG should be in the range from 100 kΩ to 1 MΩ. If Power Good function is not
used, PG pin has to remain floating.
Package information
LD39100
20/29
DocID15676 Rev 7
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
E]
BDWUM VIEW
EXPOSED PAD
PWHD \ w
—A3
9
A \
4 j m
“J
LEADS COPLANAR/TY
_ _ — — —o— — — - —‘ E
[/2
PM 1 m
J ——D/2—
p M
I SEAT/N0 PLANE
79465373
LD39100
Package information
DocID15676 Rev 7
21/29
7.1 DFN6 (3x3 mm) package information
Figure 33: DFN6 (3x3 mm) package outline
FOOTPRINT RECOMMENDED
3‘70
0.95
J
0‘50 (fix)
0.45 {6x}
79466377C
K17
Package information
LD39100
22/29
DocID15676 Rev 7
Table 7: DFN6 (3x3 mm) mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.80
1
A1
0
0.02
0.05
A3
0.20
b
0.23
0.45
D
2.90
3
3.10
D2
2.23
2.50
E
2.90
3
3.10
E2
1.50
1.75
e
0.95
L
0.30
0.40
0.50
Figure 34: DFN6 (3x3 mm) recommended footprint
Bottom view
‘_ A _‘ . r61 .
—'—Dz— WWW
m
:9 arms
I i
n m _[L
H ‘ a‘ Lb ‘
AA?
DetaiIA
09'8" A « ’ 'r-mamx mm
{ mm» mm. 1
WE . EL Z3: mm.
m (a m L HEW. m. J
E
a // ///
v / / /
// // /
/ // /
/
// // /
i0 / /
"mm W
(s) D
Top view WWW
E]
LD39100
Package information
DocID15676 Rev 7
23/29
7.2 DFN6 (3x3 mm) automotive-grade package information
Figure 35: DFN6 (3x3 mm) automotive-grade package outline
7 0.20
1.70
%Z
”@095
/
and H74
I@'
2.50
757
Package information
LD39100
24/29
DocID15676 Rev 7
Table 8: DFN6 (3x3 mm) automotive-grade mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.80
0.85
0.90
A1
0.0
0.05
b
0.20
0.25
0.30
D
2.95
3.00
3.05
D2
2.30
2.40
2.50
e
0.95
E
2.95
3.00
3.05
E2
1.50
1.60
1.70
L
0.30
0.40
0.50
Figure 36: DFN6 (3x3 mm) automotive-grade recommended footprint
E]
K0
g 0 M5
i Y 10.05
'40 ‘ 5 0.10
R w max
\
O %
"2
7 u
3 “s )
$1 n “
Id
E
m
51 2
COVER
1
— 10 SPRUCKH HULK P/TCN CUMULATIVE TOLERANCE 10,20
78759787N
LD39100
Package information
DocID15676 Rev 7
25/29
7.3 DFN6 (3x3 mm) packing information
Figure 37: DFN6 (3x3) tape outline
4.
(WW
M
10.5 ‘ ‘
700
78759737N
Package information
LD39100
26/29
DocID15676 Rev 7
Figure 38: DFN6 (3x3 mm) reel outline
Table 9: DFN6 (3x3) tape and reel mechanical data
Dim.
mm
Min.
Typ.
Max.
A0
3.20
3.30
3.40
B0
3.20
3.30
3.40
K0
1
1.10
1.20
LD39100
Ordering information
DocID15676 Rev 7
27/29
8 Ordering information
Table 10: Order code
Order code
Output voltage
Industrial grade
Automotive grade(1)
LD39100PUR
LD39100PURY
Adj. from 0.8 V
LD39100PU12R
LD39100PU12RY
1.2 V
LD39100PU18R
LD39100PU18RY
1.8 V
LD39100PU25R
LD39100PU25RY
2.5 V
LD39100PU30R
3.0 V
LD39100PU33R
LD39100PU33RY
3.3 V
Notes:
(1)Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to
AEC Q001 and Q002 or equivalent.
Revision history
LD39100
28/29
DocID15676 Rev 7
9 Revision history
Table 11: Document revision history
Date
Revision
Changes
29-Jul-2009
1
Initial release.
16-Apr-2010
2
Modified Figure 8 on page 9.
11-Oct-2011
3
Document status promoted from preliminary data to datasheet.
24-Apr-2014
4
Part numbers LD39100xx, LD39100xx12 and LD39100xx25 changed
to LD39100. Updated Table 1: Device summary. Updated the
description in cover page Section 1: Circuit schematics, Section 2:
Pin configuration, Section 4: Electrical characteristics, Section 5:
Typical performance characteristics, Figure 32: Typical application
circuit for fixed output version, Section 7: Package mechanical data.
Deleted previous Section 8: Different output voltage versions of the
LD39100xx available on request. Added Section 8: Packaging
mechanical data. Minor text changes.
01-Sep-2015
5
Updated Figure 32: Typical application circuit for fixed output version.
Minor text changes.
20-Jun-2016
6
Updated features in cover page.
Removed Table 1: Device summary.
Updated Section 6.2: "Enable function".
Added Section 8: "Ordering information" and Section 7.1: "DFN6
(3x3 mm) package information".
Minor text changes.
23-Oct-2017
7
In Table 5: "LD39100 electrical characteristics (adjustable version)":
- Updated ISC Typ. value (was 1.5)
Table 6: "LD39100 electrical characteristics (fixed version)":
- Updated ISC Typ. value (was 1.5)
Removed Figure 30: ESR required for stability with ceramic
capacitors (VOUT = 0.8 V)
Removed Figure 31: ESR required for stability with ceramic
capacitors (VOUT = 2.5 V)
Updated Section 6: "Application information"
Added Section 6.1: "External capacitors"
LD39100
DocID15676 Rev 7
29/29
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